Abstract: Embodiments of the present disclosure relate to an interconnect package, a method of forming the interconnect package, and a power module. The interconnect package includes a first insulating layer, a source connecting portion disposed on a surface of the first insulating layer and adapted to electrically connect a source pad to a substrate, a second insulating layer, and a gate connecting portion disposed between the first insulating layer and the second insulating layer and adapted to electrically connect a gate pad to the substrate.

Abstract: Embodiments of the present disclosure relate to a semiconductor package, a method of forming semiconductor package and a power module. For example, there is provided a semiconductor package. The semiconductor package may comprise a chip level having a first side and a second side opposite to the first side, wherein the chip level comprises a plurality of power transistors and each power transistor is provided with a source and a gate at the first side. Besides, the semiconductor package may also comprise a first conductive level positioned on the first side and comprising a gate connection portion electrically connected with the gate and a source connection portion electrically connected with the source.

Abstract: A semiconductor package is provided, including a package forming method and a power supply module. The semiconductor package may include a first chip comprising a first surface, and a second surface opposite the first surface. The semiconductor package may also include a chip interconnect component located on the second surface of the first chip. In addition, the semiconductor package may include a second chip located on the chip interconnect component, comprising a third surface in contact with the chip interconnect component, and a fourth surface opposite the third surface. The chip interconnect component comprises an electrically conductive frame, one side of the electrically conductive frame is electrically connected to the second surface of the first chip, and the other side of the electrically conductive frame is electrically connected to the third surface of the second chip.

Abstract: Embodiments of the present disclosure relate to a semiconductor package, a method of forming the package and an electronic device. For example, the semiconductor package may comprise a first substrate assembly comprising a first surface and a second surface opposite the first surface. The semiconductor package may also comprise one or more chips connected or coupled to the first surface of the first substrate assembly by a first thermally and electrically conductive connecting material. In addition, the semiconductor package further comprises a second substrate assembly comprising a third surface and a fourth surface opposite the third surface, the third surface and the first surface being arranged to face each other, and the third surface being connected to one or more chips by a second thermally and electrically conductive connecting material. At least one of the first surface and the third surface is shaped to have a stepped pattern to match a surface of the one or more chips.

Abstract: A method of estimating a channel response of a channel is provided that includes transforming a frequency domain signal received via the channel into a time domain signal and searching the time domain signal for a location of minimum energy. The method also includes padding the time domain signal with zeroes at the location of minimum energy and transforming the padded time domain signal to a second frequency domain signal. The second frequency domain signal is used as an estimated channel response for the channel.

Abstract: A Digitial Radio Mondiale (DRM) receiver and demodulation method includes a programmable downsampler and a programmable N-point Fast Fourier Transform (FFT) to recover and demodulate the OFDM symbols in a received DRM-encoded RF signal. The received signal is digitally sampled at a rate operably integer downsampled to achieve a number N samples in the useful portion of the OFDM symbol for input to an N-point FFT, where N equal to a power of two. The downsampling rate and size (N-points) of the FFT depend on the DRM encoding and transmission parameters, notably the robustness mode and spectrum occupancy. This reduces the processing/computational requirements and the design complexity of the DRM receiver.

Abstract: A method and apparatus for estimating a carrier frequency offset (CFO) in a Digital Radio Mondiale receiver is provided. Orthogonal frequency-division multiplexing (OFDM) demodulation is performed on a received DRM signal to produce OFDM symbols. A cell characteristic in corresponding cells in the OFDM symbols is compared and a carrier index of a frequency pilot cell in the cells is identified based upon the compared cell characteristic. The CFO is estimated based on the identified carrier index of the frequency pilot cell. The ratio of values of the cell characteristic in corresponding cells may be calculated and the frequency pilot cell identified by identifying cells for which the cell characteristic is most nearly equal. The CFO may be estimated by comparing the identified carrier index with an expected carrier index of a frequency pilot cell.

Abstract: A Digital Radio Mondiale (DRM) receiver and demodulation method includes an analog and digital separation filter for filtering and separating a DRM-encoded signal and a non DRM-encoded signal from a composite RF signal received at the receiver. The DRM receiver includes a programmable downsampler and a programmable N-point Fast Fourier Transform (FFT) to recover and demodulate the OFDM symbols in a received DRM-encoded RF signal. The received signal is digitally sampled at a rate operably integer downsampled to achieve a number N samples in the useful portion of the OFDM symbol for input to an N-point FFT, where N equal to a power of two. The downsampling rate and size (N-points) of the FFT depend on the DRM encoding and transmission parameters, notably the robustness mode and spectrum occupancy. The structure and operation of the receiver in this manner simplifies the design and reduces the required filter order of the analog and digital separation filter.

Abstract: A zero current detector for a DC-DC converter includes a first transistor having a drain, a gate, and a source for sensing the voltage of a first terminal of a power transistor; a second transistor having a drain, a gate, and a source for sensing the voltage of a second terminal of a power transistor; and a third transistor having a coupled gate and drain for receiving a reference current that is coupled to the gates of the first and second transistors and a source coupled to the source of the first transistor, wherein an output signal is provided by the drains of the first and second transistors. A load is coupled to the drains of the first and second transistors. The zero current detector also includes a fourth transistor having a current path coupled between the source of the second transistor and the second terminal of the power transistor and a gate for receiving a control signal.

Abstract: A method of gain control by amplifying an input signal with a variable gain amplifier to generate an output signal where the gain of the variable gain amplifier is selected based upon a control signal presented at a control input of the variable gain amplifier. When the output signal is larger than the upper boundary, incrementally changing the magnitude of the control signal so as to reduce the gain of the variable gain amplifier in a step-wise linear fashion. When the output signal is smaller than the lower boundary, incrementally changing the magnitude of the control signal so as to increase the gain of the variable gain amplifier in a step-wise linear fashion.

Abstract: A circuit includes an OPAMP-less bandgap voltage generating core circuit connected between a regulated voltage and a ground reference to generate an output bandgap voltage. A preregulator circuit generates the regulated voltage from an unregulated supply voltage. The preregulator circuit includes a negative feedback loop operable to stabilize the regulated voltage and a current source operable to source current for the regulated voltage, the current source mirroring a PTAT current of the OPAMP-less bandgap voltage generating core circuit. The core circuit further includes a negative feedback loop and a positive feedback loop, the negative and positive feedback loops functioning to equalize two internal voltages within the core.

Abstract: A driver for a DC-to-DC converter that may utilize a flyback or buck-boost converter circuit. The driver includes a driver circuit and an interface circuit. The interface circuit has a sensor sensing an input voltage from a DC supply and generating a sensor signal to a driver selector. The driver selector compares the sensor signal to a comparison voltage to determine the type of converter circuit and then transmits a selector signal to a driver circuit where it is used to control one or more of the components of the driver circuit, such as the logic circuit which is used for driving the converter to regulate the converter output. The sensor includes a sense resistor along with a current-sense amplifier, which is adapted for connection to a high side or a low side of a power supply while still producing a substantially equivalent output voltage or sensor signal.

Abstract: A motor driver includes an H-bridge having a first differential input, a second differential input, and a differential output; a sensing circuit coupled to the differential output of the H-bridge; a comparison and logic circuit coupled to the sensing circuit; a pair of pre-driver circuits coupled to the comparison and logic circuit for driving at least one of the differential inputs of the H-bridge; and a pair of level shifters coupled between the comparison and logic circuit and the sensing circuit. The pair of level shifters is used to assure that the VGS of a pair of serially coupled transistors in the sensing circuit do not change with temperature, motor current, or voltage, and each includes a transistor receiving a reference current. The pair of level shifters each further includes a serially coupled diode and zener diode for preventing current from flowing from the differential output of the H-bridge to the level-shifting transistor.

Abstract: A compensated regulator includes a transconductance stage having a positive input for receiving a reference voltage, a negative input, and an output, an adjustable compensation block coupled between the output of the transconductance stage and ground, a feedback circuit having a first node coupled to the output of the compensated regulator, a second node coupled to the negative input of the transconductance stage, and a third node coupled to ground, and a driver stage having an input coupled to the output of the transconductance stage, a current output coupled to the output of the compensated regulator, and a sense output coupled to the adjustable compensation block.

Abstract: A zero current detector for a DC-DC converter includes a first transistor having a drain, a gate, and a source for sensing the voltage of a first terminal of a power transistor; a second transistor having a drain, a gate, and a source for sensing the voltage of a second terminal of a power transistor; and a third transistor having a coupled gate and drain for receiving a reference current that is coupled to the gates of the first and second transistors and a source coupled to the source of the first transistor, wherein an output signal is provided by the drains of the first and second transistors. A load is coupled to the drains of the first and second transistors. The zero current detector also includes a fourth transistor having a current path coupled between the source of the second transistor and the second terminal of the power transistor and a gate for receiving a control signal.

Abstract: A differential amplifier receives a differential input signal and generates an output signal at an output node. An auxiliary circuit coupled to the differential amplifier operates to improve slew rate response. In quiescent and small signal situations with respect to the differential input signal, the auxiliary circuit does not alter or change operation of the differential amplifier. However, in situations where a large signal change is experienced with respect to the differential input signal, the auxiliary circuit functions to speed up the sourcing and sinking current to/from the output node. A stability compensation capacitor coupled to the output node is accordingly more quickly charged or discharged and an improvement in slew rate performance of the differential amplifier is experienced.

Abstract: A precise over-voltage comparator exhibits zero-waiting-current characteristics during normal working conditions. An NMOS transistor is used in conjunction with other circuit elements to regulate the over-voltage comparator. For normal power supply voltages, the comparator stays in standby status and does not consume quiescent current.

Abstract: A micro-controller is connected between a hardware-based adaptive differential pulse code modulation (ADPCM) decoder and a read only memory (ROM) storing both micro-controller programming instructions and ADPCM encoded source file data. A micro-controller architecture implements time multiplexed ROM addressing driven by a two phase clock signal. In an instruction phase, a program counter supplies ROM address(es) for retrieving micro-controller programming instructions. In a decoder phase, an address counter supplies ROM address(es) for retrieving portions of the ADPCM encoded source file data. ADPCM encoded source file data extracted from the ROM in the decoder phase of the clock signal is delivered to the decoder for processing during the subsequent instruction phase of the clock signal. The selection between program counter and address counter supplied addresses for application to the ROM is made by a two phase clock signal driven multiplexer.

Abstract: A driver for a DC-to-DC converter that may utilize a flyback or buck-boost converter circuit. The driver includes a driver circuit and an interface circuit. The interface circuit has a sensor sensing an input voltage from a DC supply and generating a sensor signal to a driver selector. The driver selector compares the sensor signal to a comparison voltage to determine the type of converter circuit and then transmits a selector signal to a driver circuit where it is used to control one or more of the components of the driver circuit, such as the logic circuit which is used for driving the converter to regulate the converter output. The sensor includes a sense resistor along with a current-sense amplifier, which is adapted for connection to a high side or a low side of a power supply while still producing a substantially equivalent output voltage or sensor signal.

Abstract: A driver for a DC-to-DC converter that may utilize a flyback or buck-boost converter circuit. The driver includes a driver circuit and an interface circuit. The interface circuit has a sensor sensing an input voltage from a DC supply and generating a sensor signal to a driver selector. The driver selector compares the sensor signal to a comparison voltage to determine the type of converter circuit and then transmits a selector signal to a driver circuit where it is used to control one or more of the components of the driver circuit, such as the logic circuit which is used for driving the converter to regulate the converter output. The sensor includes a sense resistor along with a current-sense amplifier, which is adapted for connection to a high side or a low side of a power supply while still producing a substantially equivalent output voltage or sensor signal.