Abstract: A method for hiding texture latency in a multi-thread virtual pipeline (MVP) processor including the steps of: allowing the MVP processor to start running a main rendering program; segmenting registers of various MVP kernel instances in the MVP processor according to the length set, acquiring a plurality of register sets with the same length, binding the register sets to chipsets of the processor at the beginning of the running of the kernel instance; allowing a shader thread to give up a processing time slot occupied by the shader thread after sending a texture detail request, and setting a Program Counter (PC) value in the case of return; and returning texture detail and allowing the shader thread to restart running.

Abstract: The present invention relates to a method for improving execution performance of multiply-add instructions during compiling, comprising the following steps of: compiling a source code by a compiler to acquire internal representation; optimizing; generating a machine code on the basis of a target processor, and allocating a physical register to a pseudo-register in the machine code; and improving results of register allocation to multiply-accumulate instructions. The method for improving execution performance of multiply-add instructions during compiling provided by the present invention has the following advantages: the compiler is allowed to realize procedure optimization by acquiring the optimal MAC (multiply-accumulate) instruction use gain.

Abstract: The present invention relates to a method for improving execution performance of multiply-add instructions during compiling, comprising the following steps of: compiling a source code by a compiler to acquire internal representation; optimizing; generating a machine code on the basis of a target processor, and allocating a physical register to a pseudo-register in the machine code; and improving results of register allocation to multiply-accumulate instructions. The method for improving execution performance of multiply-add instructions during compiling provided by the present invention has the following advantages: the compiler is allowed to realize procedure optimization by acquiring the optimal MAC (multiply-accumulate) instruction use gain.