Patents Assigned to Shinemore Technology Corp.
  • Patent number: 6173357
    Abstract: The present invention discloses an apparatus for combining partially defected synchronous dynamic random access memories. By selecting each memory chip with corresponding workable blocks, the partially defected SDRAMs can be combined as a workable device which can be programmed and operated in the same way as a defect-free chip. The apparatus for combining partially defected synchronous dynamic random access memory chips of the present invention includes a workable block selecting circuit and a chip selecting circuit. The workable block selecting circuit is responsive to a reference signal for selecting workable blocks of the synchronous dynamic random access memories. The chip selecting circuit is responsive to a chip selecting signal and the reference signal for selecting a chip from the synchronous dynamic random access memory chips.
    Type: Grant
    Filed: June 30, 1998
    Date of Patent: January 9, 2001
    Assignee: Shinemore Technology Corp.
    Inventor: Jiang-Tsuen Ju