Patents Assigned to Shinko Electric Industries, Ltd.
  • Publication number: 20120234589
    Abstract: A wiring substrate includes a structure in which a plurality of wiring layers are stacked through insulating layers intervening therebetween, and which has a first surface side and a second surface side, the first surface side where a semiconductor element is to be mounted, the second surface side being located at an opposite side to the first surface side, an interposer buried in an outermost one of the insulating layers located at the first surface side, and electrically connected to the semiconductor element to be mounted, and a sheet-shaped member buried in an outermost one of the insulating layers located at the second surface side, wherein, the interposer and the sheet-shaped member are disposed at symmetrical positions symmetrical each other.
    Type: Application
    Filed: March 12, 2012
    Publication date: September 20, 2012
    Applicant: SHINKO ELECTRIC INDUSTRIES., LTD.
    Inventors: Jun FURUICHI, Akihiko TATEIWA, Naoyuki KOIZUMI
  • Publication number: 20060038260
    Abstract: A conveyance system for a semiconductor wafer can be used without any change before and after a support plate is adhered to the wafer. Also, the finish accuracy of the wafer and the positioning accuracy between the wafer and the support plate can be relaxed, thus improving the manufacturing efficiency. The wafer is formed on its peripheral portion with a stepped portion, which is deeper than a finished thickness obtained by partial removal of the rear surface thereof and which can be eliminated by the partial removal of the wafer rear surface. The separation portion has a length which extends radially outward from a flat surface, and which is greater than a total sum of a maximum-minimum difference between the finish allowances of the diameters of the wafer and the support plate, and a maximum value of a positioning error between the wafer and the support plate generated upon adhesion thereof.
    Type: Application
    Filed: October 7, 2005
    Publication date: February 23, 2006
    Applicants: Renesas Technology Corp, Kabushiki Kaisha Toshiba, Shinko Electric Industries, Ltd.
    Inventors: Yoshihiko Nemoto, Masahiro Sunohara, Kenji Takahashi
  • Patent number: 6956293
    Abstract: There is provided a semiconductor device having a wafer-level package structure in which CSP structures are formed at a wafer level, which comprises a semiconductor substrate, an electrode pad formed over the semiconductor substrate, and a tail terminal formed to have an area that is smaller than the electrode pad and connected electrically to the electrode pad.
    Type: Grant
    Filed: June 4, 2003
    Date of Patent: October 18, 2005
    Assignee: Shinko Electric Industries, Ltd.
    Inventor: Eiji Takaike
  • Patent number: 6025672
    Abstract: It is an object of the invention to provide a discharge tube in which the electrical insulating property between the discharge trigger wires is not deteriorated by the sputtering substance generated when discharge is conducted between the upper and the lower discharge electrode. There are provided sub-discharge trigger wires 50 at the center of the inner circumferential wall of the airtight cylinder 10 under the condition that the sub-discharge trigger wires 50 are electrically insulated from the upper and the lower discharge electrode. At the same time, there are provided discharge trigger wires 30a connected with the upper discharge electrode and discharge trigger wires 30b connected with the lower discharge electrode in the upper and the lower portion of the inner circumferential wall of the airtight cylinder 10 at which there is no possibility of adhesion of the sputtering substance 40 generated in the process of discharging conducted by the upper and the lower discharge electrode.
    Type: Grant
    Filed: March 20, 1998
    Date of Patent: February 15, 2000
    Assignee: Shinko Electric Industries, Ltd.
    Inventor: Kazuhiko Machida