Abstract: A mathematical computation circuit to interpolate attribute values along a line between two points where the attributes are known and a video circuit using the interpolation circuit. The interpolation circuit includes a circuit to calculate the rate of change of said attribute between said two points on a raster-scanned display on a per scan line basis and a circuit to add the rate of change of said attribute per scan line to the current attribute value for the current scan line as each new scan line occurs. The sum is used as the new current value. A video system uses multiple instances of this interpolation circuit and includes a sorter to sort vertices records from a display list and send the appropriate attribute data to the interpolation circuits. There rates of change are calculated and attribute values developed for each pixel location.

Abstract: A bit serial multiplier suitable for pipelined operations. This multiplier uses a conventional bit serial multiplier cell using Booth's algorithm and stored carry architecture, but modified in several respects. First, the partial product and carry storage registers may be put in a hold state so that their contents remain constant over as many clock cycles as a stall signal is asserted so that data may be inserted in the pipeline without destroying pipeline synchronization. Second, there are added two shift registers one of which parallel loads the partial product bits and the other of which loads the carry bits as each set of bits exists after all the multiplier bits have been shifted into the multiplier. After the parallel loading process, the partial product and carry latches in the main cell are cleared thereby allowing another multiplication with different operands to begin.