Abstract: An invention is provided for using a comparand provided to a CAM for multiple CAM operations without requiring the comparand to be reloaded from a host processor for each CAM operation. The invention includes a comparand data register that is capable of storing a comparand. Associated with the comparand data register, is a plurality of result registers. In operation, the comparand is provided as input data to the CAM for a plurality of search operations. For each search operation, the result is stored in one of the plurality of result registers. In this manner, the comparand stored in the comparand data register can be reused for multiple search operations, with each result stored in a separate result register.

Abstract: A content addressable memory (CAM) is provided that can perform wide word searches. At least one CAM memory core having a plurality of bit pattern entry rows is included in the CAM. In addition, search logic is included that, is capable searching particular rows during each cycle. The search logic is also capable of allowing match line results of unsearched rows to remain unchanged during a cycle. The CAM further includes a serial AND array in communication with the bit pattern entry rows, wherein the serial AND array is capable of computing a match result for wide word entries that span multiple bit pattern entry rows. In one aspect, a match line enable signal is provided to the serial AND array, which facilitates computation of the match result.

Abstract: An invention is provided for low power searching in a CAM using sample words to save power in the compare lines. The invention includes comparing a sample section of stored data to a corresponding sample section of search data on a plurality of rows in the CAM. If a sample section of the stored data on any row of the plurality of rows is equivalent to the corresponding sample section of the search data, a remaining section of search data is allowed to propagate to the local compare lines coupled to the remaining section of the stored data of each row. However, if the sample section of the stored data is different from the corresponding sample section of the search data, the local compare lines coupled to the remaining section of the stored data on each row are latched.

Abstract: Variable width Content Addressable Memory (CAM) devices for searching data of variable widths, are disclosed. The CAM device includes a plurality of CAM blocks and a plurality of dual-mode first encoders. The plurality of CAM blocks is configured to store a plurality of data of variable widths with each data having one or more data portions of one or more predetermined widths. Each CAM block is configured to store a predetermined width portion of the data such that each data is stored in one or more CAM blocks. The CAM blocks receive a search data having a specified number of search data portions with each search data portion having one or more predetermined widths. Each CAM block receives a search data portion of the search data for searching the search data in the CAM blocks. The plurality of dual mode first encoders is configured for concatenating the specified number of the CAM blocks to generate one or more search results.

Abstract: Methods for built-in self-test (BIST) testing and circuitry for testing a content addressable memory (CAM) core are provided. In one example, the BIST circuit includes a search port for enabling searches of the CAM core and a maintenance port for enabling addressing of locations of the CAM core. The maintenance port includes writing logic for writing to locations of the CAM core. The BIST circuit also includes a BIST controller for coordinating BIST testing of the CAM core. The BIST controller is capable of performing a BIST search on the CAM core on every cycle through the search port and performing a BIST write at selected times to the CAM core. Thus, the BIST write is capable of being performed in a same cycle as the BIST search permitting at-speed BIST. The BIST controller, performs BIST testing in a manner that limits the number of rows in the CAM that match at any given cycle, thus allowing a low-power BIST operation.

Abstract: An invention is disclosed for reducing power in a CAM using sample words. A sample section of stored data is compared to a corresponding sample section of search data. If the sample section of the stored data is different from the corresponding section of the search data, a non-match result is generated. However, if the sample section of the stored data is equivalent to the corresponding sample section of the search data, the remaining section of the stored data is compared to a corresponding remaining section of the search data. Thus, the remaining section of the stored data is not compared to the corresponding remaining section of the search data if the sample section of the stored data is different from the corresponding section of the search data.

Abstract: Variable width Content Addressable Memory (CAM) devices for searching data of variable widths, are disclosed. The CAM devices include, a plurality of CAM blocks and a plurality of dual-mode first encoders. The plurality of CAM blocks is configured to store a plurality of data of variable widths with each data having one or more data portions of one or more predetermined widths. Each CAM block is configured to store a predetermined width portion of the data such that each data is stored in one or more CAM blocks. The CAM blocks receive a search data having a specified number of search data portions with each search data portion having one or more predetermined widths. Each CAM block receives a search data portion of the search data for searching the search data in the CAM blocks. The plurality of dual mode first encoders is configured for concatenating the specified number of the CAM blocks to generate one or more search results.

Abstract: An invention is disclosed for a content addressable memory (CAM) with a block select for power management. The CAM includes a plurality of memory blocks for storing data addressable within the CAM, and a search port in communication with the plurality of memory blocks. The search port is capable of facilitating search operations using the memory blocks. Also included in the CAM is a block select bus capable of selecting at least one specific memory block from the plurality of memory blocks. By using the block select bus, the search operations are performed using only the selected memory blocks. Similar to search operations, the block select signal or a similar signal can also be used to select specific memory blocks, wherein maintenance operations are performed using only the selected memory blocks.

Abstract: A priority resolver for use in a CAM circuit priority encoder is provided. The priority resolver includes one or more priority resolver sub-units. Each priority resolver sub-unit includes an local hit (pehit) generation circuitry. The local hit (pehit) generation circuitry is configured to generate pehit data. Also provided as part of a priority resolver sub-unit is a resolve processing circuit that is coupled to the local hit (pehit) generation circuitry. The resolve processing circuit is configured to receive the pehit data and an enable signal. Preferably, the resolve processing circuit includes input gating circuitry. An output differentiator and gating circuit is further provided as part of the priority resolver sub-unit and is configured to receive an output of the resolve processing circuit. In this embodiment, the priority resolver sub-unit is implemented in one or more stages of the priority resolver, and each stage is configured to include one or more priority resolver sub-units.

Abstract: A three-port content addressable memory (CAM) device and method thereof are provided. The three-port CAM device includes a CAM, a search control block, and a maintenance control block. The CAM is configured to store data. The search control block is arranged to receive search data and search control signals via a first port for searching the search data in the CAM. The search control block is further configured to perform search operations by accessing the CAM. The search operations are performed within search cycles with each search operation being performed over multiple clock cycles. In this configuration, more than one search operations are capable of being performed simultaneously over one or more clock cycles. Search results of the search operations are output via a second port. The maintenance control block is configured to perform read/write operations by reading or writing specified data in the CAM via a third port.

Abstract: A content addressable memory (CAM) is provided. The CAM includes a search port for performing search operations at each clock cycle and a maintenance port for writing and reading data to address locations of the content addressable memory. An interlock signal is also provided and is communicated from the search port to the maintenance port to establish when writing and reading of data is to be performed to the content addressable memory so that the search operations continue uninterrupted at each clock cycle. Preferably, the interlock signal is communicated at an end of a search operation and at a beginning of a search pre-charge operation. The maintenance port is configured to set-up a writing operation at a beginning of a clock cycle and execute the write operation at the end of the search operation and the beginning of the search pre-charge operation. In another preferred example, search operations can be deselected at any time, yet any desired writing and reading operation can still be executed.

Abstract: The present invention provides a CAM circuit having a redundant array and method for implementing the same. The circuit includes a first CAM array, a redundant CAM array, one or more storage devices, a first encoder, and a redundant encoder. The first CAM array stores data and has a plurality of first entries. Each first entry has a plurality of first memory cells, wherein any first entry that includes one or more defective first memory cells is defective. The redundant CAM array has one or more redundant entries of redundant memory cells. Each of the one or more redundant entries has a redundant address and is associated with a defective first entry, wherein each redundant entry is configured store data for the associated first entry. The one or more storage devices associate each of the defective first entries with a redundant entry.

Abstract: Binary and ternary content addressable memory (CAM) cells are disclosed, which permit the construction of high-performance, large-capacity CAM arrays. The CAM cells have a reduced match line power dissipation, and a reduced compare line loading that is data independent, and full swing comparator output. Match line power dissipation is limited by means of a NAND chain match line. Loading on compare lines is limited by connecting compare lines to the gate terminals of the CAM cell comparator. Local precharge devices at the output of the comparator provide full swing compare logic levels for faster matching. The same precharge devices also serve as an active reset for the comparator. Comparator circuits for ternary CAM cells further employ disable means, which makes the comparison operation conditional on the value stored in the mask memory element. The use of disable means allows the mask and data to be stored separately in a non-encoded form.