Abstract: An integrated vertical SiC—PN power diode has a highly doped SiC semiconductor body of a first conductivity type, a low-doped drift zone of the first conductivity type, arranged above the semiconductor body on the emitter side, an emitter zone of a second conductivity type, applied to the drift zone, and at least one thin intermediate layer of the first conductivity type. The intermediate layer is arranged inside the drift zone, has a higher doping concentration than the drift zone, and divides the drift zone into at least one first anode-side drift zone layer and at least one second cathode-side drift zone layer. There is also disclosed a circuit configuration with such SiC—PN power diodes.

Abstract: The invention relates to a semiconductor structure for controlling a current (I), comprising a first n-conductive semiconductor region (2), a current path that runs within the first semiconductor region (2) and a channel region (22). The channel region (22) forms part of the first semiconductor region (2) and comprises a base doping. The current (I) in the channel region (22) can be influenced by means of at least one depletion zone (23, 24). The channel region (22) contains an n-conductive channel region (225) for conducting the current, said latter region having a higher level of doping than the base doping. The conductive channel region (225) is produced by ionic implantation in an epitaxial layer (262) that surrounds the channel region (22).

Abstract: A uniform silicon carbide single crystal with either an n-type or a p-type conductivity. The crystal has a net carrier concentration less than 1015 cm?3 and a carrier lifetime of at least 50 ns at room temperature.

Abstract: An integrated vertical SiC—PN power diode has a highly doped SiC semiconductor body of a first conductivity type, a low-doped drift zone of the first conductivity type, arranged above the semiconductor body on the emitter side, an emitter zone of a second conductivity type, applied to the drift zone, and at least one thin intermediate layer of the first conductivity type. The intermediate layer is arranged inside the drift zone, has a higher doping concentration than the drift zone, and divides the drift zone into at least one first anode-side drift zone layer and at least one second cathode-side drift zone layer. There is also disclosed a circuit configuration with such SiC—PN power diodes.

Abstract: A semi-conductor structure for controlling and switching a current has a switch element and an edge element. The switch element contains a first semi-conductor area of a first conductivity type contacted by way of an anode electrode and a cathode electrode, a depletion area that is arranged inside the first semi-conductor area and that can be influenced by a control voltage applied to the control electrode for the purpose of current control, and an island area of a second conductivity type that is buried inside the first semi-conductor area. The edge element contains an edge area of the second conductivity type that is buried inside the first semi-conductive area and that is formed on a common level with the buried island area, in addition to an edge terminating area of a second conductivity type adjacent the edge area.

Abstract: The semiconductor device includes a first semiconductor region made from n-conducting SiC and a second semiconductor region made from p-conducting SiC. A Schottky contact layer electrically contacts the first semiconductor region, and an ohmic p-contact layer electrically contacts the second semiconductor region. Both contact layers consist of a nickel-aluminum material. This allows both contact layers to be annealed together without adversely effecting the Schottky contact behavior.

Abstract: A switching device for switching at a high operating voltage includes an LV switching element and a first HV switching element that are connected together in a cascode circuit. Furthermore, at least a second HV switching element is connected in series with the first HV switching element. A first protection element is connected between the HV grid terminals of the first and second HV switching elements, respectively.

Abstract: A semiconductor configuration with an ohmic contact-connection includes a p-conducting semiconductor region made of silicon carbide. A p-type contact region serves for the contact-connection. The p-type contact region is composed of a material containing at least nickel and aluminum. A substantially uniform material composition is present in the entire p-type contact region. A method for contact-connecting p-conducting silicon carbide with a material containing at least nickel and aluminum is also provided. The two components nickel and aluminum are applied simultaneously on the p-conducting semiconductor region.

Abstract: A device for mounting a substrate includes a susceptor as a support for the substrate to be coated. The susceptor includes an insert whose surface is at least partly formed by a metal carbide layer of a predetermined thickness. The device for mounting the substrate eliminates a contamination of the substrate during processing, such as during production of an epitaxial layer on a wafer. A method for producing the insert includes the steps of producing a metallic preform, embedding the metallic preform in a carbon-containing powder, heating the metallic preform and the carbon-containing powder to an elevated temperature, hard processing the heat-treated preform and disposing the hard-processed preform on the susceptor as an insert.

Abstract: A semiconductor configuration for current control has an n-type first semiconductor region with a first surface, a p-type covered island region, within the first semiconductor region, with a second surface, an n-type contact region arranged on the second surface within the island region and a lateral channel region, formed between the first and second surface as part of the first semiconductor region. The channel is part of a current path from or to the contact region. The current within the lateral channel region may be influenced by at least one depletion zone. A lateral edge of the lateral channel region extends as far as the contact region.

Abstract: J-FET having a first semiconductor region (2, 3), which comprises a first contact (7) with a highly doped contact layer (8) serving as a source disposed between two second contacts (9) serving as a gate on its first surface (4). The three contacts (7, 9) are each connected to a respective second semiconductor region (5, 6). The first and second semiconductor regions (2, 3, 5, 6) are of opposite conductivity types. The second semiconductor regions (5) connected to the second contacts (9) extend in the first semiconductor region (2, 3) below the second semiconductor region (6) that is connected to the first contact (7), with the result that the three second semiconductor regions (5, 6) at least partially overlap in a projection onto a horizontal plane and a channel region (11) is formed between the three second semiconductor regions (5, 6) in the first semiconductor region (2, 3).

Abstract: A semiconductor configuration with an ohmic contact-connection includes a p-conducting semiconductor region made of silicon carbide. A p-type contact region serves for the contact-connection. The p-type contact region is composed of a material containing at least nickel and aluminum. A substantially uniform material composition is present in the entire p-type contact region. A method for contact-connecting p-conducting silicon carbide with a material containing at least nickel and aluminum is also provided. The two components nickel and aluminum are applied simultaneously on the p-conducting semiconductor region.

Abstract: A component is produced on a substrate made of SiC. The component has at least one ohmic contact and at least one Schottky contact. The component is brought to a temperature of more than 1300° C. at least during the growth of an epitaxial layer. To ensure that the production of the ohmic contact does not lead to impairment of other structures on the component and that the ohmic contact, for its part, is insensitive with respect to later method steps at high temperatures, the first metal is applied to the substrate for the ohmic contact before the epitaxial layer is grown.

Abstract: A semiconductor structure includes at least one &agr;-silicon carbide region and an electrically insulating region, e.g. made of an oxide layer, and an interface located between them. The selection of an &agr;-silicon carbide polytype having a smaller energy gap than that of the 6H silicon carbide polytype for at least one region near the interface results in a high charge carrier mobility in this region.

Abstract: A semiconductor configuration, in particular based on silicon carbide, is specified which rapidly limits a short-circuit current to an acceptable current value. For this purpose, when a predetermined saturation current is exceeded, a lateral channel region is pinched off, and the current is limited to a value below the saturation current.

Abstract: A thin-film system is deposited onto a surface of a semiconductor region. After at least one window has been opened in the thin-film system, the window serves as a mask for a first selective processing of a first semiconductor partial region. By undercutting the thin-film system, the edge of the window is drawn back approximately uniformly by a mean undercutting depth. The at least one enlarged window serves as a mask for a second selective processing of a second semiconductor partial region. A semiconductor structure is also provided.

Abstract: A device for limiting an alternating electric current includes a least one passive semiconductor configuration and a protection circuit. The semiconductor configuration is configured such that when a forward voltage is applied thereto, a forward current flows through the semiconductor configuration. The forward current increases monotonously with the forward voltage up to a saturation current at an associated saturation voltage. At a forward voltage above the saturation voltage, the forward current is limited to a limiting current that is smaller than the saturation current. The semiconductor configuration is further configured such that when a reverse voltage is applied, a reverse current flows through the passive semiconductor configuration.