Abstract: Systems and methods for communicating on a richly-connected multiprocessor computer system using a pool of buffers for dynamic association with a virtual channel. Packets are communicated in a multiprocessor computer system having a large plurality of processing nodes interconnected by a defined interconnection topology, in which a communication from a source processing node to a target processing node may pass through one or more intermediate nodes en route to the target processing node. A set of virtual channels is associated for each link in the interconnection topology. A first subset of buffers is dedicated for fixed correspondence to virtual channel identifiers, and a second subset of buffers is dedicated for dynamic allocation and assignment to virtual channels.

Abstract: Systems and methods for arbitrating for virtual channels to prevent livelock in richly-connected multiprocessor computer system. Livelock is prevented in a multiprocessor computer system, in which each of a large plurality processing node has input links and egress links. A virtual channel is assigned to convey the communication. Communication data from the plurality of input links is buffered in cross point buffers. A subset of the cross point buffers bids for, and arbitrates, use of the same one egress link. The virtual channel of the selected communication is identified. It is determined whether any of the other communications bidding for use of the egress link are associated with the identified virtual channel and if so whether any communication has been waiting longer than the selected communication. If so, allowing that communication to use the egress link before the selected communication does.

Abstract: Systems and methods for preventing deadlock in richly-connected multiprocessor computer system using dynamic assignment of virtual channels. Deadlock is prevented in a multiprocessor computer system having a large plurality of processing nodes interconnected by a defined interconnection topology. Each link in the interconnection topology is associated with a set of virtual channels. Each virtual channel has corresponding communication buffers to store communication data and each virtual channel has an associated virtual channel identifier. Each communication between a source processing node and a target processing node is assigned an initial virtual channel to convey the communication from the source processing node. At an intermediate processing node, a different virtual channel is assigned to convey the communication toward the target processing node, in accordance with pre-defined rules to avoid a cycle of dependency of communication buffer resources.

Abstract: Computer system and method using a Kautz-like digraph to interconnect computer nodes and having control back channel between nodes. A multinode computing system includes a large plurality of computing nodes interconnected via a Kautz topology having order O, diameter n, and degree k. The order equals (k+1)kn?1; The data interconnections from a node x to a node y in the topology satisfy the relationship y=(?x*k?j) mod O, where 1?j?k; and each x,y pair includes a unidirectional control link from node y to node x to convey flow control and error information from a receiving node y to a transmitting node x.

Abstract: A mesochronous clock system and method to minimize latency and buffer requirements for data transfer in a large multiprocessor computing system. A stream of data is transferred from a first clock domain with a first clock signal to a second clock domain with a second clock signal. The first and second clock signals have a mesochronous relationship. The first clock signal is sampled in the second clock domain. In response to the sampling of the first clock signal, a modified version of the first clock signal is formed having a known phase relationship to the second clock signal. A parallel form of the received data is formed under the control of modified version of the first clock signal. In response to the sampling of the first clock signal, a subset of contiguous bits of the parallel data is selected for use in the second clock domain.

Abstract: Computer systems and methods using efficient module and backplane tiling to interconnect computer nodes via a Kautz-like digraph. A multinode computing system includes a large plurality of computing nodes interconnected via a Kautz topology having order O, diameter n, and degree k. The order equals (k+1)kn?1. The interconnections from a node x to a node y in the topology satisfy the relationship y=(?x*k?j) mod O, where 1?j?k, and the computing nodes are arranged onto a plurality of modules. Each module has an equal plurality of computing nodes on it. A majority of the inter-node connections are contained on the plurality of modules and a minority of the inter-node connections are inter-module connections. Inter-module connections are routed among modules in parallel on an inter-module connection plane.

Abstract: A multi-node computer system with a plurality of interconnected processing nodes, including a method of using DMA engines without page locking by the operating system. The method includes a sending node with a first virtual address space and a receiving node with a second virtual address space. Performing a DMA data transfer operation between the first virtual address space on the sending node and the second virtual address space on the receiving node via a DMA engine, and if the DMA operation refers to a virtual address within the second virtual address space that is not in physical memory, causing the DMA operation to fail. The method includes causing the receiving node to map the referenced virtual address within the second virtual address space to a physical address, and causing the sending node to retry the DMA operation, wherein the retried DMA operation is performed without page locking.