Abstract: An efficient implementation of DSP functions in a field programmable gate array (FPGA) using one or more computational blocks, each block having of a multiplier, an accumulator, and multiplexers. The structure implements most common DSP equations in a fast and a highly compact manner. A novel method for cascading these blocks with the help of dedicated DSP lines is provided, which leads to a very simple and proficient implementation of n-stage MAC operations.

Abstract: Methods and systems improve mapping of LUT based FPGAs. In some embodiments, a topological sort is performed on a network to be mapped, whereby the network is represented as a Directed Acyclic Graph. The system locates feasible reconvergent paths existing from transitive fan-ins of individual nodes using a Reconvergent Path Locator for replicating fan-outs of the nodes in the DAG, and therefore improves the number of LUTs and the time consumed in the mapping process.

Abstract: The present invention relates to a system for reducing the delay during technology mapping in FPGA that comprises locating and replicating the critical fan-in nodes in the mapping logic. Parallel computation is performed on the replicated nodes followed by selection of the output. The delay reduction approach in the present invention gives a highly efficient logic implementation when delay is the prime concern and area can be afforded to be expanded. The technique relies on replicating logic and performing parallel computation on delay critical LUT's.

Abstract: A FPGA comprising, a direct interconnect structure for providing selective data routing without stressing the general-purpose routing resources and enabling high rate of data exchange within the FPGA. At least two IP cores are connected to each other through said direct interconnect structure for enabling simultaneous data interaction among the ports of said IP cores and for providing configurable bus width routing between said IP cores, and a plurality of logic blocks connected to said IP cores through said direct interconnect structure for enabling simultaneous data routing among said IP cores and said plurality of logic blocks.

Abstract: An improved FPGA having a direct interconnect structure to provide selective data routing without stressing the general-purpose routing resources and to enable high rate of data exchange within the FPGA. At least two IP cores are connected to each other through the direct interconnect structure to enable simultaneous data interaction among the ports of the IP cores and to provide configurable bus width routing between the IP cores, and a plurality of logic blocks connected to the IP cores through the direct interconnect structure to enable simultaneous data routing among the IP cores and the plurality of logic blocks.

Abstract: A FPGA device that includes a plurality of programmable logic blocks connected to each other through interconnect resources, one or more sets of registers connected to the interconnect resources for configuring the programmable logic blocks. Additional logic is provided with the registers for selecting an interconnect/logic block testing mode thereby enabling a rapid interconnect/logic testing.

Abstract: The present invention relates to a system for reducing the delay during technology mapping in FPGA that comprises locating and replicating the critical fan-in nodes in the mapping logic. Parallel computation is performed on the replicated nodes followed by selection of the output. The delay reduction approach in the present invention gives a highly efficient logic implementation when delay is the prime concern and area can be afforded to be expanded. The technique relies on replicating logic and performing parallel computation on delay critical LUT's.

Abstract: An interconnect structure enables indirect routing in programmable logic. The structure includes a domain comprising a plurality of routing lines and an input line connected to a first routing line in the domain. A switch box is connected to the first routing line and is configured to indirectly connect the input line to the other routing lines in the domain. In some embodiments a domain includes programmable switches that are configured to connect a routing line of one domain to any routing line of the other domains.

Abstract: A configurable logic device configured to add or subtract inputs using a carry signal with a fixed value of 0 is described. In embodiment(s), inputs are received by a device. The device is configured to add or subtract the inputs using a carry signal that has a fixed value of logic 0. The device is further configured to provide an output that has a value of the sum or the difference of the received inputs.

Abstract: The present invention relates to a system for reducing the delay during technology mapping in FPGA that comprises locating and replicating the critical fan-in nodes in the mapping logic. Parallel computation is performed on the replicated nodes followed by selection of the output. The delay reduction approach in the present invention gives a highly efficient logic implementation when delay is the prime concern and area can be afforded to be expanded. The technique relies on replicating logic and performing parallel computation on delay critical LUT's.

Abstract: A method and system for improved optimal mapping of LUT based FPGA's. The invention comprises performing a topological sort on the network to be mapped, whereby the network is represented in form of a Directed Acyclic Graph. The system locates feasible reconvergent paths existing from transitive fan-ins of each node using a Reconvergent Path Locator for replicating fan-outs of the nodes in the DAG, and therefore optimizing the number of LUT's and the time consumed in the mapping process.

Abstract: An interconnect structure enables indirect routing in programmable logic. The structure includes a plurality of routing lines, and switch box(es) and connection boxes coupled to the plurality of routing lines. The connection boxes include at least one programmable switch in each routing track. The position of the programmable switch(es) in each connection box connected to same interconnect matrix differs from the position of said programmable switch(es) in corresponding routing tracks of other connection boxes thereby utilizing the connectivity of said switch box for input connections and increasing the flexibility of connections.

Abstract: The configurable logic device provides enhanced flexibility, scalability and area efficient implementation of arithmetic operation on (N?1) bit variables. The device includes a first configurable logic subsystem capable of generating logic OR output in response to functions of N?1 input variables in arithmetic mode, a second configurable logic subsystem capable of generating logic AND output in response to functions of N?1 input variables in arithmetic mode, and a configurable logic block connected at its first input to the output of the first configurable logic subsystem, connected at its second input to the output of the second configurable logic subsystem, connected at its third input to the Nth input variable, and connected at its fourth input to a carry/borrow signal.

Abstract: An improved method and apparatus for reloading frames in which errors are detected during the Programmable Logic Device configuration. A configuration data frame for a FPGA is loaded to the Frame register of the FPGA and also to an error detection circuit which detects errors with the loaded frame. An error counter value is maintained by the apparatus and is incremented each time an error with a frame is detected. The incremented value is compared by a Comparator circuit with a pre-determined threshold value ‘n’. If a match is found then the configuration process is aborted, else the data frame is reloaded in the configuration memory, transferred again to the frame register and rechecked for errors. If no error is detected with the reloaded frame, the error counter value is reset and the next frame is loaded until the FPGA configuration process is over.

Abstract: A field programmable device is disclosed, including a plurality of logic blocks; a plurality of connections connecting the logic blocks; configuration circuitry for outputting configuration data for programming the field programmable device, the configuration circuitry providing at least one pair of outputs; and error detection circuitry for comparing the outputs to determine if there has been a configuration error.

Abstract: A Programmable Logic Device provides efficient scalability for configuration memory programming while requiring reduced area for implementation. The device includes an array of configuration memory cells, a Vertical Shift Register (VSR) connected to the vertical lines of the array of configuration memory cells, a Select Register (SR) connected to the horizontal lines of the array of configuration memory cells, a Horizontal Shift Register (HSR) providing the enable input to the Select Register (SR), and a Configuration State Machine (CSM) which synchronizes the operations of the VSR, SR and HSR.

Abstract: A method for mapping an electronic digital circuit to a Look Up table (LUT) based Programmable Logic Deviceoperates by selecting an unmapped or partially mapped LUT, and identifying a group of circuit elements for mapping on the selected LUT based on the available capacity of the selected LUT and the mapping constraints. The identified circuit elements are mapped onto the selected LUT. The identification of circuit elements and mapping is carried out while taking into consideration the Cascade Logic associated with the selected LUT. The process continues until all circuit elements have been mapped. The group of circuit elements is mapped to the cascade logic prior to mapping on the LUTs. Conversely, the cascade logic is incorporated only after all circuit elements have initially been mapped onto LUTs or some elements remain unmapped after all LUTs have been utilized. The mapping constraints include timing, placement, and size constraints.