Abstract: A data processing unit is disclosed with a register file having a plurality of registers. A memory having a plurality of n-bit input/output ports, and a coupling unit for coupling the memory with the register file, a memory address and select unit for addressing the memory banks are provided. The coupling unit comprises a bus having a bus width of at least 2n-bits forming at least a first and second sub-bus, first couplers for coupling each memory bank or the register file selectively with one of the sub-busses, and second couplers for coupling the register file or the memory banks with the bus.

Abstract: The present invention relates to a system and method for compensating IC parameters. According to an embodiment of the present invention, a die of an IC wafer is coupled with a compensation circuit that classifies the die into various types. Examples of types include fast, typical, and slow. The assigned type may be used in a special oscillator that compensates for variations from a die to a predetermined criteria. According to an embodiment of the present invention, a slow die directs a signal that moves through a relatively short path, a fast die directs a signal that moves through a relatively long path, and a typical die directs a signal that moves through a relatively medium length path in the compensation circuit. Accordingly, each die on a wafer may be coupled with a compensation circuit such that the compensation circuit selects a path of a circuit that adjusts the frequency produced by the dies to produce a batch of ICs that would meet the predetermined criteria for the vast majority of the dies.

Abstract: A semiconductor integrated circuit device including a redundant metal line for replacing a non-operational metal line for connecting to a circuit block. The invention further includes a method for decoupling a defective or otherwise non-operational conductive data line from a circuit block to which it is connected, and replacing the defective conductive data line with a redundant line by coupling it to the same circuit block. A spare conductive block is not needed. The redundant metal lines may be used in multiple levels of hierarchy within an integrated circuit device.

Abstract: The present invention is related to a filter circuit that allows preamplifiers, such as those used in hard disk drives, to quickly recover from transients such transients caused by power switching, write to read switching, and thermal asperity. According to an embodiment of the present invention, under normal conditions, such as signals at 100 KHz to 10 MHz, signals at medium frequencies, such as signals at 100 KHz to 10 MHz, pass through a low pass filtering circuit. When a transient signal is received, then a change in voltage for Vout of the low pass filtering circuit increases by more than 100*Vout. For example, during transient conditions, the low pass filter circuit may also pass signals ranging from 10 MHz to 100 MHz. Accordingly, under transient conditions, the low pass pole moves approximately 100 times or more. A feedback loop subtracts the resulting low pass signals from the original signal, acting as a high pass filter.

Abstract: An arrangement of enhanced drivability transistors is disclosed herein which includes a plurality of conductor patterns, wherein the conductor patterns include ring-shaped portions which enclose device diffusion contacts and the ring-shaped portions form the gate conductors of insulated gate field effect transistors (IGFETs).

Abstract: A write circuit for facilitating a write head for writing to a memory in a computer is described. The write circuit includes a supply voltage source configured to provide current to the write circuit. The write circuit further includes a current source coupled to the supply voltage source, the current source configured to maintain the current at a predetermined value. The write circuit further includes a switch coupled to the current source, the switch being configured to bypass the current source during a time when the current is changing.

Abstract: A shading film of chrome is formed entirely on one surface of a circular substrate of quartz. The substrate is rotated and resist is applied to the shading film. Since the substrate is shaped in a circle, the resist spreads uniformly on the entire surface of the shading film by the centrifugal force. Therefore, the resist has a substantially uniform film thickness over almost the entire surface of the shading film. This resist is patterned to form a resist pattern. By etching the shading film with the resist pattern used as a mask, a pattern preferable in accuracy of dimensions can be formed.

Abstract: A method for fabricating a shallow trench isolation structure involves several steps. The steps of an illustrative method include forming a first resist pattern on a substrate, etching the substrate to form a shallow trench therein using the first resist pattern as a mask, removing the first resist pattern from the substrate, depositing an oxide layer on the substrate including in the shallow trench, depositing a polish stop layer on the oxide layer, forming a second resist pattern on a portion of the polish stop layer substantially covering the shallow trench using the same mask as the mask for the first resist pattern, etching the polish stop layer, removing the second resist pattern leaving the portion of the polish stop layer substantially covering the shallow trench, polishing the oxide layer using the portion of the polish stop layer substantially covering the shallow trench as a polish stop, and removing the portion of the polish stop layer substantially covering the shallow trench.

Abstract: A metal interconnect layer that fills in a via hole formed by first depositing a first Al--Cu film on the sidewalls of the via hole at a low temperature and a low sputtering power and then depositing a second Al--Cu film on the first Al--Cu film at a high temperature and high sputtering power. Sputtering is performed in two steps at low and high temperatures within the same sputtering chamber. The deposition at low temperature and low sputtering power provides good coverage in the via hole, and the deposition at high temperature and high sputtering power reduces the process time.

Abstract: A semiconductor structure comprises first gate conductors which wrap around N-wells of buried-channel P-type metal oxide semiconductor field effect transistors and second gate conductors which do not wrap around P-wells of surface-channel N-type metal oxide semiconductor field effect transistors and a method of manufacturing the same comprises forming insulators adjacent each of the N-wells and the P-wells, protecting the N-wells with a patterned mask, forming first divots in areas of the insulators adjacent the N-wells and forming second divots in areas of the insulators adjacent P-wells, wherein the first divots have a greater depth than the second divots.

Abstract: A method of forming a trench capacitor comprises steps of forming a trench in a substrate, partially filling the trench with a first conductive material, lining a portion of the trench above the first conductive material with a collar material, etching the collar material to a strap depth below a top of the trench, and filling the trench with a second conductive material, wherein a portion of the second conductive material positioned between the strap depth and the top of the trench comprises a buried strap.

Abstract: Improved techniques for driving wordlines of a semiconductor memory device are described. Accordingly to the invention, a wordline 402 is driven by a wordline driver 406 at a first end and then provided with a small amount of additional circuitry 442 at the other end of the wordline. When the additional circuitry senses that the wordline is beginning to transition to an active state, the additional circuitry operates to assist or accelerate the transition of the wordline to the active state. Accordingly, the invention operates to rapidly transition wordlines to an active state while using only minimal amounts of die area. The invention is particularly well suited for dynamic random access memories.

Abstract: Semiconductor chips are produced from a wafer. The semiconductor chips are separated from one another by etching the wafer all the way through, by a dry etching process, in defined separation zones between the semiconductor chips. Initially, first etching trenches for separating the p-n junctions are etched into the wafer. Then, second etching trenches are etched from the opposite side of the wafer until the individual semiconductor chips are completely separated.

Abstract: An end-wall frame for an LED alphanumeric display circuit board provides full-length accurate standoffs for the display to prevent cracking and crazing of the epoxy coating of the encapsulated device, eliminates the need to apply black paint to the non-display portions of the lens, and provides a device for accurately aligning the printed circuit board in the lensed area.

Abstract: By using a monolithic sheet of photodetector semiconductor and creating a series of isolated individual optical paths, the performance of a multiple channel coupler can be improved. Multiple photodetectors are fabricated on the substrate, yielding electro-optically matched devices. By using common connection of the photodetectors and common connection of the optical sources, the pin-per-channel count is minimized.

Abstract: A closed mold for encapsulating LED alphanumeric display devices uses opposing platens and top and bottom plates to achieve a seal about the display device. By providing the display device with a dambar, splatter on the leads is avoided.

Abstract: An optical send-receive module includes a frame which has a front section, a back side, and a top section. A lens carrier is attached to the front section of the frame. The lens carrier includes one or more lenses which face forward. An integrated circuit carrier is placed within the top section of the frame. First metal leads electrically connect components within the lens carrier to an integrated circuit within the integrated circuit carrier. Second metal leads extend from the integrated circuit carrier, along the top section of the frame, down the back side of the frame and are bent under the frame.

Abstract: A circuit for discharging of a photovoltaic power source has a first and a second terminal and the circuit comprises a discharge circuit which is connected between the first and second terminal of the power source which comprises a controllable current source which is controlled by a band gap reference.

Abstract: A programmable fuse element disposed between integrated circuit elements that may be selectively joined during the manufacture or programming of an integrated circuit. The fuse element is a normally open fuse that electrically isolates the integrated circuit elements. The fuse element is comprised of a central area of conductive material insulated from the integrated circuit elements by areas of dielectric material. The integrated circuit elements and the fuse element are disposed on a thin oxide layer covering a semiconductor substrate to prevent those elements from shorting to the semiconductor substrate or to each other via the semiconductor substrate. A protective dielectric layer may be deposited over both the fuse element and the integrated circuit elements during the manufacture of the overall integrated circuit. A laser beam is used to burn through the protective layer and melts both the conductive material and the dielectric material that form the fuse element.

Abstract: An optically-triggered silicon controlled rectifier (SCR) (21) having a number of semiconductor layers (23, 24, 31) diffused into an N type substrate (22). Specifically, the SCR is formed by diffusing a first P+ layer (23) into an upper surface of the substrate. Then, an N+ layer (24) is diffused into a portion of an upper surface of the first P+ layer. An oxide layer (25) which is permeable to optical radiation is formed on the first P+ layer. A conductive cathode terminal (26) is then deposited on the N+ layer. Therefore, a trench (30) is etched in the lower surface of the substrate. The trench is defined by a depth and a surface. A second P+ layer (31) is diffused into the surface of the trench. The depth of the trench substantially defines a spacing between the first and second P+ layers. The chip is soldered onto a pedestal (33) formed on a lead frame (34). The solder is deposited in the trench and contacts the second P+ layer to form an anode terminal (36).