Abstract: A method and circuit for exploiting the characteristics of the ZBTSI algorithm by using the relationship of the data octet and the octets adjacent thereto to detect error conditions such as violations of the DS1 ones density criteria for detection of transmission channel errors in the ZBTSI decoder. This relationship provides an optimized partial error correction technique which minimizes error multiplication in the PCM transmission channels.

Abstract: In accordance with the present invention a plurality of input control data bits are added to a plurality of input telecommunications transmission channels in the form of an input control word wherein any of the individual data bits can be changed without adversely effecting the ability of the system to synchronize and recover the added control word from the multiplexed data stream at the receiving end. A service channel is thus provided. The synchronization circuit described by the present invention is particularly useful in telecommunications transmission of a large plurality of communication channels as is the case in fiber optic transmission wherein a single control word may be useful, for example, as an alarm with respect to one or more of the multiplex telecommunications channels. In a preferred embodiment of the invention, an 8 Kbit/sec control channel is described.

Abstract: A center frequency high resolution digital phase-lock loop circuit (CF HRDPLL) is described with an input clock reference frequency which is equal to the output phase-locked frequency. The output is derived from delaying the input clock a variable number of gate delays ranging from no delay to one period of the input clock. A shift register controls the number of gate delays. A 360 degree phase detector initializes the shift register to provide no delay when the output is delayed by almost one period of the input clock and a phase retard correction occurs. An advance correction from a no delay condition causes a fast shift to occur to locate one period of delay while the output is held at no delay. The output is then switched to slightly less than one period of phase delay to allow further phase advance corrections to occur. Gate delay variations due to process, voltage and temperature are compensated for to provide a relatively constant clock phase correction.

Abstract: The present invention comprises a circuit for providing both B8ZS and B6ZS coding and decoding selectably with a single circuit. A rate control signal can, in preferred embodiment, be utilized to select the desired line code in a application dependent manner. Advantage is taken of the fact that there is a commonality in B8ZS and B6ZS code patterns in the last five bits of the codes, with the difference being the number of logic "zeros" before the first bit of coding.

Abstract: A counter slip control circuit is described for digital transmission systems wherein the counter uses a feedback circuit to define the permissible counter states. The slip control input modifies the feedback function so that certain counter states are either repeated or skipped. A repeated counter state is equivalent to retardation of the counter output signal phase. A skipped counter state is equivalent to advancing the counter output signal phase. The slip control gate is eliminated from the clock input line to the counter and instead is included in the feedback path which eliminates the skew problem and permits the equivalent of adding clock pulses without the requirement for logic speeds of twice the normal clock speed.

Abstract: The present invention describes a circuit which allows a data stream to be scrambled by continuously running uninterrupted Pseudo Random sequence without multiplying errors. This is accomplished by allowing a register in the Pseudo Random scrambling receiver to acquire synchronization with a register in the Pseudo Random scrambling transmitter such that the two registers run independently through the same maximal length Pseudo Random sequence without further need for communication with each other. Bit errors occurring between the transmitter and receiver do not cause the scrambling registers at the two ends to become out of synchronization and they remain in synchronism unless a timing slip occurs to cause the transmitter and receiver to lose synchronization.