Abstract: An example of a radio frequency (RF) transmitter system for communication may include a transmit pre-distortion module configured to provide a second transmit calibration signal during a transmit calibration mode based on a first transmit calibration signal and one or more transmit calibration adjustment signals. The one or more transmit calibration adjustment signals may include an offset parameter associated with DC offset and an imbalance parameter associated with at least one of gain and phase imbalances. The system may include a transmit channel frequency converter coupled to the transmit pre-distortion module. The transmit channel frequency converter may be configured to provide a fourth transmit calibration signal during the transmit calibration mode based on a third transmit calibration signal and a transmit reference signal.

Abstract: An example of a method for off-line calibration of a radio frequency (RF) communication system may include one or more of the following: enabling an off-line calibration mode for an RF communication system; generating an off-line calibration signal; applying to a frequency converter a first off-line calibration signal corresponding to the generated off-line calibration signal; translating the first off-line calibration signal into a second off-line calibration signal; evaluating one or more calibration adjustment signals associated with the calibration signal to reduce error in the communication system, wherein the one or more calibration adjustment signals may include an offset parameter associated with DC offset and an imbalance parameter associated with at least one of gain and phase imbalances; storing one or more calibration adjustment signals; disabling the off-line calibration mode; applying a communication signal; and adjusting the communication signal based on the stored one or more calibration adjus

Abstract: A chip assembly may comprise a substrate having a top surface and a bottom surface. The chip assembly may comprise a first die having a circuit surface and a connecting surface, the circuit surface comprising one or more integrated circuits. The chip assembly may comprise a chip-scale frame having an inside surface, an outside surface, and a well region, the well region having an opening within the inside surface, the well region having a wall, the well region housing the first die, the first die attached to the wall by a first coupling mechanism, the inside surface coupled to the top surface of the substrate by a second coupling mechanism. The chip assembly may comprise a heat sink coupled to the outside surface of the chip-scale frame using a third coupling mechanism.

Abstract: An interpolation circuit for comparing an input voltage signal with an interpolated reference signal derived from a first reference voltage signal and a second reference voltage signal may include a transconductive circuit configured to generate a first differential current signal proportional to a difference between the first reference voltage signal and the input voltage signal and a second differential current signal proportional to a difference between the second reference voltage signal and the input voltage signal, an intermediate circuit configured to generate a third differential current signal, and a transinductive circuit configured to generate an output voltage signal having a first polarity if a value of the input voltage signal is greater than a value of the interpolated reference signal and a second polarity if the value of the input signal is less than the value of the interpolated reference signal.

Abstract: An example of a radio frequency (RF) receiver system for communication may include a receive channel frequency converter configured to provide a second receive calibration signal during a receive calibration mode based on a first receive calibration signal and a receive reference signal. The system may include a receive pre-distortion module coupled to the receive channel frequency converter. The receive pre-distortion module may be configured to provide a fourth receive calibration signal during the receive calibration mode based on a third receive calibration signal and one or more receive calibration adjustment signals. The one or more receive calibration adjustment signals may comprise an offset parameter associated with DC offset and an imbalance parameter associated with at least one of gain and phase imbalances.

Abstract: High-speed, high-performance, low-power transponders, serializers and deserializers are disclosed. A serializer may include a serdes framer interface (SFI) circuit, a clock multiplier unit, and a multiplexing circuit. A deserializer may include an input receiver circuit for receiving and adjusting an input data signal, a clock and data recovery circuit (CDR) for recovering clock and data signals, a demultiplexing circuit for splitting one or more data channels into a higher number of data channels, and a serdes framer interface (SFI) circuit for generating a reference channel and generating output data channels to be sent to a framer. The input receiver circuit may include a limiting amplifier. Each of the serializer and deserializer may further include a pseudo random pattern generator and error checker unit. The serializer and deserializer each may be integrated into its respective semiconductor chip or both may be integrated into a single semiconductor chip.

Abstract: Examples of a system and method for sigma-delta analog-to-digital conversion of an electrical input signal are disclosed. A bandpass-filtered signal based on an electrical input signal and an analog feedback signal may be provided. A multi-bit digital representation of the bandpass-filtered signal may be provided. An analog representation of the multi-bit digital representation may be provided. A return-to-zero (RTZ) carving operation may be performed on the analog representation to obtain the analog feedback signal.

Abstract: An example of a radio frequency (RF) receiver system for communication may include a receive channel frequency converter configured to provide a second receive calibration signal during a receive calibration mode based on a first receive calibration signal and a receive reference signal. The system may include a receive pre-distortion module coupled to the receive channel frequency converter. The receive pre-distortion module may be configured to provide a fourth receive calibration signal during the receive calibration mode based on a third receive calibration signal and one or more receive calibration adjustment signals. The one or more receive calibration adjustment signals may comprise an offset parameter associated with DC offset and an imbalance parameter associated with at least one of gain and phase imbalances.

Abstract: An example of a method for off-line calibration of a radio frequency (RF) communication system may include one or more of the following: enabling an off-line calibration mode for an RF communication system; generating an off-line calibration signal; applying to a frequency converter a first off-line calibration signal corresponding to the generated off-line calibration signal; translating the first off-line calibration signal into a second off-line calibration signal; evaluating one or more calibration adjustment signals associated with the calibration signal to reduce error in the communication system, wherein the one or more calibration adjustment signals may include an offset parameter associated with DC offset and an imbalance parameter associated with at least one of gain and phase imbalances; storing one or more calibration adjustment signals; disabling the off-line calibration mode; applying a communication signal; and adjusting the communication signal based on the stored one or more calibration adjus

Abstract: An example of a radio frequency (RF) transmitter system for communication may include a transmit pre-distortion module configured to provide a second transmit calibration signal during a transmit calibration mode based on a first transmit calibration signal and one or more transmit calibration adjustment signals. The one or more transmit calibration adjustment signals may include an offset parameter associated with DC offset and an imbalance parameter associated with at least one of gain and phase imbalances. The system may include a transmit channel frequency converter coupled to the transmit pre-distortion module. The transmit channel frequency converter may be configured to provide a fourth transmit calibration signal during the transmit calibration mode based on a third transmit calibration signal and a transmit reference signal.

Abstract: A radio frequency transceiver for off-line transmit and receive calibrations includes: a transmit pre-distortion module configured to receive a transmit calibration signal during a transmit calibration mode, a transmit communication signal during a transmit communication operation mode, and one or more transmit calibration adjustment signals; a transmit channel frequency converter; and a transmit calibration module configured to provide the one or more transmit calibration adjustment signals and the transmit calibration signal to the transmit pre-distortion module.

Abstract: A chip assembly includes a chip, a paddle, an interface layer, a frequency extending device, and lands. The chip has contacts. The interface layer is disposed between the chip and the paddle. The frequency extending device has at least a conductive layer and a dielectric layer. The conductive layer has conductive traces. The frequency extending device is disposed adjacent to the side of the chip and overlying the paddle. The lands are disposed adjacent to the side of the paddle. The contacts are connected to the conductive traces. The conductive traces are connected to the lands. The frequency extending device is configured to reduce impedance discontinuity such that the impedance discontinuity produced by the frequency extending device is less than an impedance discontinuity that would be produced by bond wires each having a length greater than or substantially equal to the distance between the contacts and the lands.

Abstract: A communication system includes a multiplexer configured to multiplex a first set of data channels into a first data channel and to multiplex a second set of data channels into a second data channel, and a delay adjuster configured to adjustably delay the first data channel based on a delay adjust command. The communication system also includes a first amplifier configured to amplify the delayed first channel into a first output data channel, and a second amplifier configured to amplify the second data channel into a second output data channel. The communication system further includes a first driver configured to convert the first output data channel into a first drive signal to drive an optical modulator, and a second driver configured to convert the second output data channel into a second drive signal to drive the optical modulator.

Abstract: A fractional-N synthesized chirp generator includes a fractional-N synthesizer and a digital ramp synthesizer. The fractional-N synthesizer has a frequency synthesizer and a sigma-delta modulator module. The fractional-N synthesizer is configured to receive a reference frequency input signal and a frequency control value. The fractional-N synthesizer is configured to transform the reference frequency signal and the frequency control value to a chirped radio frequency (RF) output signal in a deterministic manner. The digital ramp synthesizer is configured to receive the reference frequency input signal and configured to generate the frequency control value utilizing the reference frequency input signal. The digital ramp synthesizer is further configured to provide the frequency control value to the fractional-N synthesizer. The frequency control value varies with time.

Abstract: A channelization filter communication system comprises: a channelization filtering system, a calibration unit, amplifiers, communication channel frequency converters and a baseband processor. The channelization filtering system includes a selector input configured to receive a communication channel filter selector signal and selectable communication channel filter elements. The selectable communication channel filter elements include one or more resistors formed of a first resistor type and one or more capacitors formed of a first capacitor type. The calibration unit includes a calibration signal generator configured to provide a calibration signal and a frequency measurement unit. The calibration signal generator includes one or more resistors formed of the same first resistor type and one or more capacitors formed of the same first capacitor type.

Abstract: An encoding and/or decoding communication system comprises a framer interface, an encoder, a multiplexer, an output driver, and a clock multiplier unit (CMU). The encoder includes an input latch circuitry stage; an output latch circuitry stage; an intermediate latch circuitry stage interposed between the input latch circuitry stage and the output latch circuitry stage, the intermediate latch circuitry stage coupled to the input latch circuitry stage and the output latch circuitry stage; a plurality of encoding logic circuitry stages interposed between the input latch circuitry stage and the output latch circuitry stage, a last one of the plurality of encoding logic circuitry stages placed adjacent to the output latch circuitry stage and coupled to the output latch circuitry stage; and a feedback between the output latch circuitry stage and the last one of the plurality of encoding logic circuitry stages.

Abstract: High-speed, high-performance, low-power transponders, serializers and deserializers are disclosed. A transponder may include a transmitter and a receiver. A serializer may include (i) a serdes framer interface (SFI) circuit for receiving data channels and a reference channel from a framer and realigning the data channels, (ii) a clock multiplier unit (CMU) for receiving a clock frequency and translating the clock frequency to a higher clock frequency, (iii) a multiplexing circuit for merging data channels into one data channel, (iv) an output driver stage, (v) a reference selection circuit for selecting a reference clock, filtering the reference clock, and providing to the CMU one of the selected reference clock or a filtered reference clock.

Abstract: A radio frequency transceiver for off-line transmit and receive calibrations includes: a transmit pre-distortion module configured to receive a transmit calibration signal during a transmit calibration mode, a transmit communication signal during a transmit communication operation mode, and one or more transmit calibration adjustment signals; a transmit channel frequency converter; and a transmit calibration module configured to provide the one or more transmit calibration adjustment signals and the transmit calibration signal to the transmit pre-distortion module.

Abstract: An integrated circuit includes a serdes framer interface (SFI) circuit for receiving a first set of data channels and a reference channel, generating first logic levels for the first set of data channels, and realigning the first set of data channels relative to a reference channel. The integrated circuit further includes a multiplexing circuit for receiving a second set of data channels and for merging the second set of data channels into one or more data channels. The second set of data channels is generated based on the first set of data channels. A data rate of the one or more data channels is higher than a data rate of the second set of data channels.

Abstract: A communication system includes a front-end multi-throw switch, a back-end multi-throw switch, multiple filters and a switch controller. The front-end multi-throw switch includes front-end throws and a front-end pole. The front-end pole is coupled to a receive channel or a transmit channel. The front-end pole is switchably coupled to one of the front-end throws. The back-end multi-throw switch includes back-end throws and a back-end pole. Each of the back-end throws is associated with a corresponding one of the front-end throws. The back-end pole is coupled to the receive channel or the transmit channel. The back-end pole is switchably coupled to one of the back-end throws. The one of the back-end throws corresponds to the one of the front-end throws. The filters are interposed between the front-end multi-throw switch and the back-end multi-throw switch. Each of the filters has a first port coupled to one of the front-end throws and a second port coupled to one of the back-end throws.