Abstract: The present invention is directed to providing a phase detector capable of establishing phase-locked-loop operation in a highly accurate and reliable manner. For example, exemplary embodiments detect a phase difference between at least two input signals to phase lock the input signals to one another. Exemplary embodiments include two phase detectors each of which receives the two input signals (e.g., three-state phase detectors), and each of which is forced to operate outside of its dead-band region by introducing predetermined phase delays for its inputs. Each of the two phase detectors detects a phase difference between its respective inputs. The two phase differences are then combined to produce a composite output signal formed as a net charge proportional to the net phase difference detected by the two phase detectors.

Abstract: A power supply self adjusted circuit that can sense a power supply voltage and detect whether the power supply is of a first value (e.g., 5V) or a second value (e.g., 3.3 V). In the case of a modem system, the power supply self adjusted circuit then adjusts the modem system accordingly. Hence, using this circuit, a modem or other signal processing circuit can be designed to work for both 5V and 3.3V power supply systems, for example. Futhermore, the power supply self adjusted circuit enables a modem system to automatically adjust itself when the power supply is switched from 5V to 3.3V or vice versa, without any manual intervention from the user. This capability is important for increasingly-popular PC Card- modems.

Abstract: A single pin integrated oscillator circuit includes an amplifier having a first input terminal to which an external crystal may be connected, and a second input terminal which receives a feedback path from an output terminal of the amplifier. An oscillator output signal having a relatively large voltage swing is provided from the first input terminal through a buffer. The oscillator operates over a wide range of voltages and process variations, and it can accept an input signal from an external crystal or can accept any clock signal having a swing of approximately 1 V.

Abstract: A logic converter enables a digital logic product to work with either an ECL signal input or a TTL signal input without any need of modifying or reconfiguring the product. In particular, the logic converter converts digital input signals of a first logic type (for example, ECL) to digital output signals of a third logic type (for example, CMOS). It also converts digital input signals of a second logic type (for example, TTL) to digital output signals of the third logic type. A first operational transconductance amplifier circuit including a first differential amplifier using a differential transistor pair of a first conduction type receives digital input signals of the first logic type and converts the digital input signals to digital output signals of the third logic type.

Abstract: The output stage of a differential operational amplifier includes a source follower amplifier and a common source amplifier which are driven by two complementary outputs of a differential input stage. Continuous-time feedback circuits are provided to set the quiescent biasing conditions accurately. The differential operational amplifier has a low output impedance and a large output voltage swing with negligible open loop gain degradation when the size of the load resistance is varied. Floating compensation capacitors reduce the total capacitor value and the physical area needed for the operational amplifier.

Abstract: A CMOS operational amplifier comprises an output gain stage including output transistors coupled between the rails so that for a given amount of current, the output transistors have rail-to-rail gate-to-source voltages. The output transistors can be made smaller in size with the output stage being capable of driving a small resistive load with minimal signal distortion.

Abstract: An exponential analog-to-digital converter comprises two gain stages, each of which includes a binary-weighted capacitor array. The capacitors are switched in succession to multiply the gain of a sampled analog input signal, while a counter counts down for each switching step from an initial setting of binary 111. When the gain signal has a value outside a predetermined reference voltage range, a 3-bit binary digital word representative of the analog input signal sample is registered in the counter. If the gain signal produced after all the capacitors have been switched in to provide the maximum gain does not fall outside the reference range, then the binary word stored in the counter for the sample of the analog signal is 000.