Abstract: Systems and techniques are disclosed for relative age tracking for entries in a buffer. For example, some techniques may include pre-computing age matrix entries of an age matrix corresponding to invalid entries of a data buffer based on a validity indication (e.g., a valid bit mask), wherein the validity indication identifies valid entries in the data buffer and the age matrix tracks relative ages of the entries in the data buffer; responsive to data being received for storage in the data buffer, selecting an entry corresponding to an index value in the data buffer from among a set of invalid entries of the data buffer; storing the data in the entry corresponding to the index value; and updating the validity indication to indicate that the entry corresponding to the index value is valid.

Abstract: Cache circuitry may be configured to receive a first message to downgrade a permission associated with data stored in a current level cache. For example, the current level cache could be a level two (L2) cache. The cache circuitry could receive the first message from a processor core having a level one (L1) cache. The cache circuitry may forward the first message to a higher level cache. For example, the higher level cache could be a level three (L3) cache. The cache circuitry may downgrade the permission associated with data stored in the current level cache based on receiving a second message from the higher level cache. The cache circuitry may forward the first message before receiving the second message and downgrading the permission. The second message may cause downgrade of the permission in multiple caches (e.g., the L1, L2, and L3 caches).

Abstract: A method for re-triggering wakeup to handle time skew between a scalar operation and a vector operation is provided. The method includes: initiating, before a Load-Store (LST) pipeline completes an execution of a load operation corresponding to a vector micro-operation (uop) dispatched to a baler issue queue, a respective load operation in a Load (LD) pipeline corresponding to the vector uop; triggering a speculative wakeup from the LD pipeline during an execution of the respective load operation; triggering a second wakeup corresponding to the speculative wakeup from the LD pipeline; and waking up, based on the second wakeup, the vector micro-operation in the baler issue queue of the baler unit.

Abstract: A method for renaming architectural register, such as control and status register (CSR), is disclosed. The method includes decoding an instruction for updating CSR, updating the CSR based on a respective instruction of the one or more instructions, allocating a unique tag to the instruction in pipeline, and writing the tag into a mapping table for renaming the CSR. The tag can identify the CSR included in the instruction or the updated values of the CSR. The tag can be associated with a unique value. Moreover, the method can employ a First In, First Out (FIFO) queuing technique and virtual bits.

Abstract: Systems and methods are disclosed for concurrent support for multiple cache inclusivity schemes using low priority evict operations. For example, some methods may include, receiving a first eviction message having a lower priority than probe messages from a first inner cache; receiving a second eviction message having a higher priority than probe messages from a second inner cache; transmitting a third eviction message, determined based on the first eviction message, having the lower priority than probe messages to a circuitry that is closer to memory in a cache hierarchy; and, transmitting a fourth eviction message, determined based on the second eviction message, having the lower priority than probe messages to the circuitry that is closer to memory in the cache hierarchy.

Abstract: Systems and methods are disclosed for memory protection for memory protection for gather-scatter operations. For example, an integrated circuit may include a processor core; a memory protection circuit configured to check for memory protection violations with a protection granule; and an index range circuit configured to: memoize a maximum value and a minimum value of a tuple of indices stored in a vector register of the processor core as the tuple of indices is written to the vector register; determine a range of addresses for a gather-scatter memory instruction that takes the vector register as a set of indices based on a base address of a vector in memory, the memoized minimum value, and the memoized maximum value; and check, using the memory protection circuit during a single clock cycle, whether accessing elements of the vector within the range of addresses will cause a memory protection violation.

Abstract: An agent may be configured to invoke a first eviction operation that is interruptible by probe operations when receiving a first type of eviction message and invoke a second eviction operation in which probe operations are interruptible by the second eviction operation when receiving a second type of eviction message. In some implementations, the agent may maintain a data storage that is inclusive of at least one of unique or dirty cache blocks in a cache maintained by an agent that transmits the second type of eviction message. In some implementations, the agent may prevent a cache block from transitioning from a modified state to an exclusive state when the agent invokes the second eviction operation to evict the cache block. In some implementations, the agent may convert from the second eviction operation to the first eviction operation when receiving the second type of eviction message.

Abstract: An integrated circuit for translating and reverse-translating the address included in a memory request is disclosed. The integrated circuit may first comprise a processor, a first boundary function, a second boundary function, and a component device. The processor is configured to transmit a memory request to a target module over a bus of the integrated circuit. The memory request requests access to one or more memory mapped resources and the memory request includes a physical address. The first boundary function is configured to translate the physical address to a relative address which operates in or applies to a different address space than an address space that the physical address operates in or applies to. The second boundary function is configured to translate the relative address to the physical address. The device is configured utilize the physical address transmitted by the second boundary function.

Abstract: A trace circuitry may be configured to receive a selection of one or more types of events possible in a processor core among multiple types of events. The trace circuitry may generate a message including trace information when an event corresponding to the selection occurs in the processor core. The trace information may include an address associated with the event and an indication of the type of event and/or cause for why the event occurred. In some implementations, the trace circuitry may use an event filter to pass events corresponding to the one or more types of events that are selected and block events corresponding to one or more types of events that are not selected. In some implementations, the trace circuitry may generate timestamps based on events to enable measurements between the events.

Abstract: A method for executing vector iota (viota) operation is disclosed. The method includes fetching a viota instruction, decoding the viota instruction into multiple viota micro-operations (uops), computing a first element viota value of a respective viota uop, determining a respective last element viota value of the respective viota uop based on the first element viota value of the respective uop, and writing the respective last element viota value of the respective viota uop to an allocated physical register. Each viota uop of the multiple viota uops has multiple elements, and each element has a viota value corresponding to a sum of active mask bits of preceding elements of the viota uops. The multiple elements of each viota uop comprise at least a first element that has a starting bit position of a respective uop and a last element that has an ending bit position of the respective uop.

Abstract: Apparatus and methods for processing of a vector load or store micro-operation with mask information as a no-operation (no-op) when a mask vector for the vector load or store micro-operation has all inactive mask elements or processing vector load or store sub-micro-operation(s) with active mask element(s) are described. An integrated circuit includes a load store unit configured to receive load or store micro-operations cracked from a vector load or store operation, determine that a mask vector for the vector load or store micro-operation is fully inactive, and process the vector load or store micro-operation as a no-operation. If the mask vector is not fully inactive, the vector load or store micro-operation is unrolled into vector load or store sub-micro-operation(s) which have active mask element(s). Vector load or store sub-micro-operation(s) which have inactive mask element(s) are ignored.

Abstract: Cache circuitry may be configured to receive a first message to downgrade a permission associated with data stored in a current level cache. For example, the current level cache could be a level two (L2) cache. The cache circuitry could receive the first message from a processor core having a level one (L1) cache. The cache circuitry may forward the first message to a higher level cache. For example, the higher level cache could be a level three (L3) cache. The cache circuitry may downgrade the permission associated with data stored in the current level cache based on receiving a second message from the higher level cache. The cache circuitry may forward the first message before receiving the second message and downgrading the permission. The second message may cause downgrade of the permission in multiple caches (e.g., the L1, L2, and L3 caches).

Abstract: Described are methods, logic, and circuitry which prevent translation lookaside buffer probing. Reporting a privilege violation fault is delayed for a defined period of time. The defined period of time can be a time frame needed to perform a long page table walk, which can be at least hundreds of clock cycles. A counter or a forced page table walk corresponding to the defined period of time can be used to implement the delay.

Abstract: Prefetch circuitry may be configured to transmit a message to cancel a prefetch of one or more cache blocks of a group. The message may correspond to a prefetch message by indicating an address for the group and a bit field for the one or more cache blocks of the group to cancel. In some implementations, the message may target a higher level cache to cancel prefetching the one or more cache blocks, and the message may be transmitted to the higher level cache via a lower level cache. In some implementations, the message may target a higher level cache to cancel prefetching the one or more cache blocks, the message may be transmitted to a lower level cache via a first command bus, and the lower level cache may forward the message to the higher level cache via a second command bus.

Abstract: First agent circuitry may receive from a second agent a first request and a first set of one or more bits. The first request may be part of a data operation. The first agent circuitry may transmit to the second agent a message including a first response to the first request, the first set of one or more bits, a second request, and a second set of one or more bits. The second set of one or more bits may be generated by the first agent circuitry to transmit state information about the second request. In some implementations, a set of one or more wires may be generated for transmission of the second set of one or more bits. The first agent circuitry may receive from the second agent a second response to the second request and the second set of one or more bits.

Abstract: An integrated circuit design may be generated for an integrated circuit. The integrated circuit design may include an instance of a module description that describes a functional operation of a module. The instance may include an input that is internal to the integrated circuit design. The integrated circuit design may be encoded in an intermediate representation (IR) data structure. A parameter may be received indicating that the input should be exposed to a simulator. The IR data structure may be compiled to produce a register-transfer level (RTL) data structure. The RTL data structure may encode a logic description associated with the instance. The parameter may be used to permit a simulator to access a node in the RTL data structure that is associated with the input.

Abstract: An integrated circuit design may be generated for an integrated circuit. The integrated circuit design may include an instance of a module description that describes a functional operation of a module. The integrated circuit design may be encoded in an intermediate representation (IR) data structure. A parameter comprising metadata associated with the instance may be received. A compiler may compile the IR data structure to produce a register-transfer level (RTL) data structure. The RTL data structure may encode a logic description associated with the instance. Compiling the IR data structure may include associating the parameter comprising metadata with the logic description.

Abstract: Described are systems and methods for clock gating components on a system-on-chip. A processing system includes one or more cores, each core including a clock gating enable bit register which is set by software when an expected idle period of the core meets or exceeds a clock gating threshold, and a power management unit connected to the one or more cores. The power management unit configured to receive an idle notification from a core of the one or more cores and initiate clock gating a clock associated with the core when the core and additional logic is quiescent and the clock gating enable bit register is set. The clock gating threshold is a defined magnitude greater than a clock wake-up time.

Abstract: An integrated circuit design may be generated for an integrated circuit. The integrated circuit design may include an instance of a module description that describes a functional operation of a module. The instance may include an input and an output. The integrated circuit design may be encoded in an intermediate representation (IR) data structure. Parameters may be received indicating that the instance should be replaced with a simulation model. The parameters may include a first parameter pointing to the instance and a second parameter pointing to the simulation model.

Abstract: Described are systems and methods for power management. A processing system includes one or more cores and a connected power management unit (PMU). The PMU is selected from one of: a first level PMU which can power scale a; a second level PMU which can independently control power from a shared cluster power supply to each core of two or more cores in a cluster; a third level PMU where each core includes a power monitor which can track power performance metrics of an associated core; and a fourth level PMU when a complex includes multiple clusters and each cluster includes a set of the one or more cores, the fourth level PMU including a complex PMU and a cluster PMU for each of the multiple clusters, the complex PMU and cluster PMUs provide two-tier power management. Higher level PMUs include power management functionality of lower level PMUs.