Abstract: Prediction circuitry may generate a vector length prediction associated with a configuration instruction prior to completion of execution of the configuration instruction. The vector length prediction may indicate a number of data elements on which a vector instruction will operate. In some implementations, the prediction circuitry can generate the vector length prediction by detecting a repeating pattern of vector lengths associated with earlier executions of the configuration instruction. In some implementations, the prediction circuitry can generate the vector length prediction by detecting decrements of an application vector length by a constant value.

Abstract: Described are systems and methods for power management. A processing system includes one or more cores and a connected power management unit (PMU). The PMU is selected from one of: a first level PMU which can power scale a; a second level PMU which can independently control power from a shared cluster power supply to each core of two or more cores in a cluster; a third level PMU where each core includes a power monitor which can track power performance metrics of an associated core; and a fourth level PMU when a complex includes multiple clusters and each cluster includes a set of the one or more cores, the fourth level PMU including a complex PMU and a cluster PMU for each of the multiple clusters, the complex PMU and cluster PMUs provide two-tier power management. Higher level PMUs include power management functionality of lower level PMUs.

Abstract: Systems and methods are disclosed for concurrent support for multiple cache inclusivity schemes using low priority evict operations. For example, some methods may include, receiving a first eviction message having a lower priority than probe messages from a first inner cache; receiving a second eviction message having a higher priority than probe messages from a second inner cache; transmitting a third eviction message, determined based on the first eviction message, having the lower priority than probe messages to a circuitry that is closer to memory in a cache hierarchy; and, transmitting a fourth eviction message, determined based on the second eviction message, having the lower priority than probe messages to the circuitry that is closer to memory in the cache hierarchy.

Abstract: Systems and methods are described for a flexible and selectable power management interface. The flexible and selectable power management interface can provide multiple power management interfaces which are selectable based on a selected processor IP core, a selected power management controller, and a variety of factors. The flexible and selectable power management interface can be a direct handshake hardware interface, a memory-mapped bus interface, or a combination of the direct handshake hardware interface and the memory-mapped bus interface.

Abstract: Systems and methods are disclosed for page table entry caches with multiple tag lengths. For example, an integrated circuit (e.g., a processor) includes a page table walk circuitry including a page table entry cache, in which the page table walk circuitry is configured to access a multi-level page table, and in which a first entry of the page table entry cache combines a first number of multiple levels and a second entry of the page table entry cache combines a second number of multiple levels that is different from the first number of multiple levels.

Abstract: Cache circuitry may be configured to receive a first message to downgrade a permission associated with data stored in a current level cache. For example, the current level cache could be a level two (L2) cache. The cache circuitry could receive the first message from a processor core having a level one (L1) cache. The cache circuitry may forward the first message to a higher level cache. For example, the higher level cache could be a level three (L3) cache. The cache circuitry may downgrade the permission associated with data stored in the current level cache based on receiving a second message from the higher level cache. The cache circuitry may forward the first message before receiving the second message and downgrading the permission. The second message may cause downgrade of the permission in multiple caches (e.g., the L1, L2, and L3 caches).

Abstract: An integrated circuit comprises a processor core including a processor pipeline configured to execute instructions; a register configured to store a power dial value that indicates a portion of available clock cycles for throttling of instruction flow through the processor pipeline; and an instruction throttling circuit configured to periodically stall removal of instructions from a queue in the processor pipeline for a number of clock cycles that is determined based on the power dial value.

Abstract: A system may include a processor having a pipeline, a plurality of counters, and trigger circuitry. The plurality of counters may mount events associated with processing instructions in the pipeline. Counters of the plurality of counters may count different events. The trigger circuitry may trigger a performance measurement for a first instruction after counters of the plurality of counters meet predefined values. Triggering the performance measurement may cause the plurality of counters to reset and then count events associated with processing the first instruction. In some implementations, the trigger circuitry may trigger the performance measurement based on an AND selection and/or an OR selection of multiple counters of the plurality of counters meeting predefined values.

Abstract: Systems and methods are disclosed for cycle accurate tracing of vector instructions. For example, a system may include a vector unit in communication with a scalar core. The vector unit may include a vector instruction queue that receives vector instructions from the scalar core. The vector unit may also include a vector execution unit that executes vector instructions from the vector instruction queue. The system may also include checkpoints in the vector unit including a first checkpoint including circuitry that sets a first bit for a first clock cycle in which a first vector instruction exits the vector instruction queue, and a second checkpoint including circuitry that sets a second bit for a second clock cycle in which a second vector instruction exits the vector execution unit.

Abstract: Systems and methods are disclosed for supporting multiple vector lengths with a configurable vector register file. For example, an integrated circuit (e.g., a processor) includes a data store configured to store a vector length parameter; a processor core including a vector register, wherein the processor core is configured to: while a first value of the vector length parameter is stored in the data store, store a single architectural register of an instruction set architecture in the vector register; and, while a second value of the vector length parameter is stored in the data store, store multiple architectural registers of the instruction set architecture in respective disjoint portions of the vector register. For example, the integrated circuit may be used to emulate a processor with smaller vector registers for the purpose of migrating a thread to a processor core of the integrated circuit for continued execution.

Abstract: Prediction circuitry may generate a vector length prediction associated with a configuration instruction prior to completion of execution of the configuration instruction. The vector length prediction may indicate a number of data elements on which a vector instruction will operate. In some implementations, the prediction circuitry can generate the vector length prediction by detecting a repeating pattern of vector lengths associated with earlier executions of the configuration instruction. In some implementations, the prediction circuitry can generate the vector length prediction by detecting decrements of an application vector length by a constant value.

Abstract: An integrated circuit for translating and reverse-translating the address included in a memory request is disclosed. The integrated circuit may first comprise a processor, a first boundary function, a second boundary function, and a component device. The processor is configured to transmit a memory request to a target module over a bus of the integrated circuit. The memory request requests access to one or more memory mapped resources and the memory request includes a physical address. The first boundary function is configured to translate the physical address to a relative address which operates in or applies to a different address space than an address space that the physical address operates in or applies to. The second boundary function is configured to translate the relative address to the physical address. The device is configured utilize the physical address transmitted by the second boundary function.

Abstract: A first circuitry may be configured to generate a first output based on an input and send an indication responsive to detection of an error while the first output is generated. A second circuitry may be configured to generate a second output based on the input. A wrapper circuitry may be configured to compare the first output and the second output to check correctness by default, and responsive to receipt of the indication, select the second output as a system output without checking for correctness by comparing the first output and the second output. In some implementations, the second circuitry may be configured to send a second indication responsive to detection of a second error while the second output is generated. The wrapper circuitry may be configured to, responsive to receipt of the second indication, ignore the check for correctness.

Abstract: Systems and methods are disclosed for store-to-load forwarding for processor pipelines. For example, an integrated circuit (e.g., a processor) for executing instructions includes a processor pipeline; a store queue that has entries associated with respective store instructions that are being executed, wherein an entry of the store queue includes a tag that is determined based on a virtual address of a target of the associated store instruction; and store-to-load forwarding circuitry that is configured to: compare a first virtual address of a target of a first load instruction being executed by the load unit to respective tags of one or more entries in the store queue; select an entry of the store queue based on a match between the first virtual address and the tag of the selected entry; and forward data of the selected entry in the store queue to be returned by the first load instruction.

Abstract: A system may generate an annotation based on an attribute determined in connection with logic. In some implementations, the logic may be between a first function (e.g., a first point of logic, such as an encoder) and a second function (e.g., a second point of logic, such as a decoder) in a first level circuit representation. The attribute may indicate, for example, fault protection using error correction code, parity, or Gray code, or a power level, frequency domain, or clock domain. The system may then identify circuitry in a second level circuit representation corresponding to the annotated logic in the first level circuit representation. The second level circuit representation may be generated based on the first level circuit representation. The system may then mark the identified circuitry in the second level circuit representation having the attribute. In some implementations, the system may determine a fault profile of an integrated circuit design based on the marking.

Abstract: Prefetchers can have improved ability to make predictions in the presence of speculative execution. The prefetcher can maintain a training queue of addresses and can predict an address for a prefetch request based on the addresses in the training queue. The addresses in the training queue can be marked to distinguish addresses associated with speculatively-executed instructions from addresses associated with non-speculatively-executed instructions. If the speculation is determined to be incorrect, the prefetcher can remove the speculative addresses from the training queue, and if the speculation is determined to be correct, the prefetcher can remove the marking from the addresses associated with speculatively-executed instructions. The prefetcher can also pause prefetching during speculative execution.

Abstract: Prefetchers can have improved ability to make predictions in the presence of speculative execution. The prefetcher can maintain a training queue of addresses and can predict an address for a prefetch request based on the addresses in the training queue. The addresses in the training queue can be marked to distinguish addresses associated with speculatively-executed instructions from addresses associated with non-speculatively-executed instructions. If the speculation is determined to be incorrect, the prefetcher can remove the speculative addresses from the training queue, and if the speculation is determined to be correct, the prefetcher can remove the marking from the addresses associated with speculatively-executed instructions. The prefetcher can also pause prefetching during speculative execution.

Abstract: Systems and methods are disclosed for processor crash analysis using register sampling. For example, an integrated circuit may include a processor core configured to execute instructions, wherein the processor core includes a program counter register and an exception program counter register (e.g., a machine exception program counter register) that is configured to store a program counter value that was current when an exception occurred; a data store connected to the exception program counter register via an ingress port that is configured to store a copy of an exception program counter value responsive to retirement of an instruction; and an exception program counter capture register, configured to store an exception program counter value from the second data store responsive to a reset signal for the processor core.

Abstract: Systems and methods are described for a flexible and selectable power management interface. The flexible and selectable power management interface can provide multiple power management interfaces which are selectable based on a selected processor IP core, a selected power management controller, and a variety of factors. The flexible and selectable power management interface can be a direct handshake hardware interface, a memory-mapped bus interface, or a combination of the direct handshake hardware interface and the memory-mapped bus interface.

Abstract: The present application relates to devices and components, including apparatus, systems, and methods for scheduling delivery and execution of page fault or permission fault exceptions. A memory management unit may receive a virtual address associated with an execution mode and initiate a virtual-to-physical translation operation. The MMU may detect a first condition associated with a search of the virtual address in a translation lookaside buffer (TLB). In response to the detection of the first condition, MMU may start a timer. MMU may detect a fault exception associated with the translation operation of the virtual address and determine that a second condition is satisfied. In response to detecting the second condition, the MMU or the reorder buffer exception monitor may deliver the fault exception based on the timer.