Abstract: An integrated level shifter circuit converts an input signal having a first voltage potential to an output signal having a second voltage potential. The level shifter circuit provides circuit operation between the sections when the voltage potential of the input logic signal is converted to the output logic signal having lower voltage potential. For logic signals transmitted between sections of an integrated circuit operating with different supply voltages. The level shift circuit for each input includes two transistors and a voltage divider circuit having two resistors in series. The values of the resistors are selected to yield a desired output voltage at a node between the two resistors. In effect, the resistors lessen a full 0.9 volt diode drop to yield a level shift which is a fraction of a diode drop. A capacitor in parallel with the resistor provides a path for AC signals and increases both the speed and bandwidth of the level shifter.

Abstract: A current mode logic circuit having npn transistors coupled to an NMOS current source provides a substantially constant current when controlled by an opamp comparator. A gate of the NMOS current source is directly coupled to an output terminal of the opamp. A source of the NMOS transistor is connected to one of the inputs of the comparator opamp. Another input terminal is connected to voltage source. The opamp compares the two inputs and provides an output signal which ensures that the opamp will provide a substantially constant current source.

Abstract: A method of producing a bipolar transistor includes the step of providing a sacrificial mesa over a layer of SiGe in order to prevent a polysilicon covering layer from forming over a predetermined region of the SiGe layer forming the transistor base. After an etching process removes the sacrificial mesa and the SiGe layer is exposed, an oppositely doped material is applied over top of the SiGe layer to form an emitter. This makes it possible to realize a thin layer of silicon germanium to serve as the transistor base. This method prevents the base layer SiGe from being affected, as it otherwise would be using a conventional double-poly process.

Abstract: A mixer is designed to operate from a low voltage power source connected via a power terminal and ground and includes a balanced mixer circuit with a balanced input port for receiving local oscillator signals, and a pair of input terminals. A biasing circuit includes, an active voltage divider connected between the power terminal and ground to provide higher and lower voltages at first and second voltage taps. A differential driver circuit includes first and second transistors, collectors of which are each direct coupled to separate ones of the pair of input terminals. The first transistor has a base coupled via a capacitor to a single ended receive signal terminal, and an emitter coupled via a first resistor to ground. The second transistor has a base coupled via a capacitor to grounds, and an emitter coupled via a second resistor to the single ended receive signal terminal. The single ended receive signal terminal is also coupled with ground via an impedance element, in one example third resistor.