Abstract: A memory management device includes a pre-fetch circuit, a setting circuit and a mapping circuit. The pre-fetch circuit acquires original data via a direct memory access (DMA) circuit, wherein the original data indicates a mapping relation between a first virtual address and multiple physical addresses. The setting circuit analyzes the original data to sequentially map the physical addresses to multiple second virtual addresses including the first virtual address and issues a write request. The mapping circuit stores a mapping relation between the physical addresses and the second virtual addresses as a first mapping table according the write request, and utilizes the first mapping table according to at least one read request corresponding to at least one channel of the DMA circuit to access the memory.

Abstract: A voltage detection device includes: a reference voltage latch circuit, outputting one of a first set of reference voltages and a second sets of reference voltages lower than the first set of reference voltages, as a third set of reference voltages according to a selection signal, and being selectively to be reset or to continue outputting the one of the first and second sets of reference voltages as the third set of reference voltages according to a first detection signal; a first voltage detector, generating the first detection signal according to a fourth set of reference voltages lower than or equal to the first set of reference voltages and an input voltage; a second voltage detector, generating a second detection signal according to the third set of reference voltages and the input voltage; and a digital circuit, generating the selection signal according to the second detection signal.

Abstract: An intelligent processing device includes a first memory, a second memory, a memory management circuit and a convolution operation circuit. The memory management circuit transfers an input data from an external memory to the first memory. The convolution operation circuit reads the input data from the first memory, and performs multiple stages of calculations to generate multiple sets of feature map data. After a first data tile of a first feature map data is generated, the memory management circuit stores the first data tile to the second memory. When a data amount of the first data tile stored satisfies a predetermined value, the memory management circuit transfers the first data tile from the second memory to the first memory, and the convolution operation circuit reads the first data tile from the first memory and accordingly performs a second-stage calculation to generate a second data tile of a second feature map data.

Abstract: A post driver includes an input pair circuit, a protection circuit, a common mode sensing circuit and an amplifier. The input pair circuit outputs a first signal through a first node and outputs a second signal through a second node according to a first input signal and a second input signal. The protection circuit provides the input pair circuit with voltage protection according to multiple first bias voltages and a second bias voltage, transmits the first signal to a first load to generate a first output signal, and transmits the second signal to a second load to generate a second output signal. The common mode sensing circuit senses a level of the first node and a level of the second node to generate a feedback signal. The amplifier generates the second bias voltage according to a reference signal and the feedback signal.

Abstract: An image processing device includes a three-dimensional noise reduction (3D NR) circuit, an artificial intelligence noise reduction (AI NR) circuit, a weight determination circuit and an image blending circuit. The 3D NR circuit performs a 3D NR operation on input image data to generate first image data. The AI NR circuit performs an AI NR operation on the input image data to generate second image data. The weight determination circuit outputs a blending weight according to a motion index. The image blending circuit blends the first image data and the second image data according to the blending weight to generate output image data.

Abstract: The present invention discloses a neural network optimization method. An operator to be replaced is selected from multiple operators in a network layer according to a predetermined condition, and the operator to be replaced is replaced by multiple equivalent operators according to a calculation function corresponding to the operator to be replaced, wherein the multiple equivalent operators include a target operator. Pre-calculating is performed for a first operator among the multiple equivalent operators, and the calculation result is inputted into the target operator. A second operator is identified according to data change conditions of the multiple equivalent operators, and the second operator is combined with the target operator to complete optimization of a neural network model. The present invention can further perform lossless conversion of the operators in the neural network, further improving calculation performance on the basis of a simplified network structure.

Abstract: The present invention discloses a processor control method including: controlling a processor to execute a first operating system in a first state; when the processor executing the first operating system satisfies a predetermined condition, controlling the processor to switch from the first state to a second state; and controlling the processor to execute a second operating system in the second state, wherein an authority of the first state is higher than an authority of the second state.

Abstract: A data transmission control device is provided. The data transmission control device is disposed in a chip that includes a Peripheral Component Interconnect Express (PCIe) interface, and the data transmission control device is coupled to a memory that includes a block. The data transmission control device includes: a control circuit, a PCIe interface controller, and an address monitoring circuit. The PCIe interface controller is configured to receive a data. The address monitoring circuit is configured to issue an interrupt to the control circuit when the data is written to the block.

Abstract: An image processing device performs a filtering operation on image data according to a set of filter data, and includes a data reconstruction circuit, a memory and an intelligent processor. The data reconstruction circuit reconstructs data of blocks in the image data to generate first reconstruction data, and reconstructs the set of filter data to generate second reconstruction data. The memory stores the first reconstruction data and the second reconstruction data. The intelligent processor executes a depthwise convolution operation according to the first reconstruction data and the second reconstruction data to generate feature map data. Two adjacent of the multiple blocks have partially same data, and quantities of columns in the second reconstruction data are associated with a channel count of the depthwise convolution operation.

Abstract: An intelligent processor includes a first operation unit and a second operation unit. The first operation unit acquires first input data corresponding to a first operator, divides the first input data into multiple sets of first sub input data, and operates the first operator to perform an operation on the first sub input data to obtain first sub output data corresponding to each set of first input data. The second operation unit uses the first sub output data as second input data of the second operator, and operates the second operator to perform an operation on the second input data to obtain second output data corresponding to each set of second input data. Thus, the second operator need not wait until the first operator finishes all operations of the first input data, allowing two adjacent operator to achieve partial parallel calculation and improving operation efficiency.

Abstract: The present disclosure provides an image processing circuit including a neural network processor, a background processing circuit and a blending circuit. The neural network processor is configured to process input image data to determine whether the input image data has a predetermined object so as to generate to heat map. The background processing circuit blurs the input image data to generate blurred image data. The blending circuit blends the input image data and the blurred image data according to the heat map to generate output image data.

Abstract: An image processing method includes the following steps: performing first guided filtering on a target data to generate a first base layer data; generating a first detail layer data according to the target data and the first base layer data; performing second guided filtering on the first base layer data to generate a second base layer data; generating a second detail layer data according to the first base layer data and the second base layer data; converting the target data, the first base layer data or the second base layer data to obtain a converted base layer data; converting the first detail layer data and the second detail layer data to respectively generate a first converted detail layer data and a second converted detail layer data; and adding the converted base layer data and the first and second converted detail layer data to obtain an output data.

Abstract: A voltage mode transmitter circuit includes a low-dropout (LDO) regulator and an output circuit. The LDO regulator generates a driving voltage. The output circuit generates an output signal, and includes: a termination resistor, transmitting the output signal; a data processing circuit, driven by the driving voltage and adjusting a level of a node according to first and second data signals; a pre-emphasis circuit, transmitting a supply voltage to the node according to a control signal to adjust a transition edge of the output signal; a voltage protection circuit, providing an overvoltage protection according to a bias voltage, and coupling the node to the termination resistor. The data processing circuit, the pre-emphasis circuit, and the voltage protection circuit include at least one transistor, and a highest level of the output signal is higher than a withstand voltage of the at least one transistor.

Abstract: An audio processing apparatus having an echo canceling mechanism is provided. An audio transmission circuit receives an input digital audio signal from an external device. A DAC circuit performs conversion according to the input digital audio signal to generate an output analog audio signal to an external display device for power amplification and playback. An ADC circuit performs analog-to-digital conversion on an amplified signal generated by a power amplification circuit and a received audio signal generated by an audio receiving device to generate an amplified digital signal and a received digital audio signal. A processor implements an echo canceling algorithm to perform echo cancellation according to the amplified digital signal and the received digital audio signal to generate an output digital audio signal to be transmitted to the external device through the audio transmission circuit.

Abstract: A video data processing apparatus provided according to one embodiment of the present invention includes a processor and a blending circuit. The processor provides a first set of parameters according to a first channel identification signal and a second set of parameters according to a second channel identification signal. The blending circuit blends a first image into first video data at a first timing according to the first set of parameters and a second image into second video data at a second timing according to the second set of parameters. A time difference between the first timing and the second timing is less than a frame period of the first video data.

Abstract: A device for detecting the movement of object in images includes a weight determination circuit, an image blending circuit, and an object movement detection circuit. The weight determination circuit determines multiple weights according to an input image and a background image, each weight corresponding to a pixel position. The image blending circuit blends the input image and the background image based on the weights to generate an updated background image. The object movement detection circuit performs a sum of absolute difference (SAD) calculation, block by block, with the input image and the background image or the updated background image to generate a moving object indication data. The object movement detection circuit generates an object movement signal according to the moving object indication data and at least one threshold. Each block contains multiple pixels.

Abstract: A video processing circuit coupled to an external memory and for generating a video stream is provided. The external memory stores a part of a first frame. The video processing circuit includes a memory, a control circuit, an image processing circuit, and a video encoding circuit. The control circuit is used for reading a first image block from the external memory and storing the first image block in the memory, the first image block being a part of the first frame. The image processing circuit is used for reading the first image block from the memory and processing the first image block to generate a second image block which is a part of the second frame different from the first frame. The video encoding circuit is used for reading the first image block from the memory and encoding the first image block to generate a part of the video stream.

Abstract: A data dividing method applied to a computing device that performs a convolution operation based on an input image data and a weight data is provided. The method includes: determining a restriction condition in connection with the performing of the convolution operation by the computing device; determining a set of candidate data blocks for the input image data and a set of candidate data blocks for the weight data according to the restriction condition; generating an evaluation result by evaluating, according to candidate data blocks in the set of candidate data blocks for the input image data and the set of candidate data blocks for the weight data, an amount of data load of the computing device in accessing both an external memory and an internal memory of the computing device; and determining a method of dividing the input image data and the weight data according to the evaluation result.

Abstract: A multichip system includes a transmitter-end chip and a receiver-end chip. The transmitter-end chip includes a first port. The receiver-end chip includes a second port. The first port is connected to the second port, and an operating mode of the first port is different from an operating mode of the second port. When the transmitter-end chip is coupled to the receiver-end chip without through another chip, the transmitter-end chip determines a first target address of the receiver-end chip with respect to the transmitter-end chip according to the operating mode of the first port, and transfers a command to the receiver-end chip according to the first target address, such that the receiver-end chip executes the command.

Abstract: A level shifter includes a low-level adjustment circuit, a comparator circuit, and a high-level adjustment circuit. The low-level adjustment circuit pulls down a level of one between a first input node and a second input node to a first low supply voltage. The comparator outputs a one having higher level between the level of the first input node and a second low supply voltage to a first output node, wherein the second low supply voltage is higher than the first low supply voltage. The high-level adjustment circuit selectively adjusts the level of the first output node according to the level of the first input node and the level of the second input node to generate an output signal.