Abstract: A memory management device includes a pre-fetch circuit, a setting circuit and a mapping circuit. The pre-fetch circuit acquires original data via a direct memory access (DMA) circuit, wherein the original data indicates a mapping relation between a first virtual address and multiple physical addresses. The setting circuit analyzes the original data to sequentially map the physical addresses to multiple second virtual addresses including the first virtual address and issues a write request. The mapping circuit stores a mapping relation between the physical addresses and the second virtual addresses as a first mapping table according the write request, and utilizes the first mapping table according to at least one read request corresponding to at least one channel of the DMA circuit to access the memory.

Abstract: A voltage detection device includes: a reference voltage latch circuit, outputting one of a first set of reference voltages and a second sets of reference voltages lower than the first set of reference voltages, as a third set of reference voltages according to a selection signal, and being selectively to be reset or to continue outputting the one of the first and second sets of reference voltages as the third set of reference voltages according to a first detection signal; a first voltage detector, generating the first detection signal according to a fourth set of reference voltages lower than or equal to the first set of reference voltages and an input voltage; a second voltage detector, generating a second detection signal according to the third set of reference voltages and the input voltage; and a digital circuit, generating the selection signal according to the second detection signal.

Abstract: An audio player device includes a digital-to-analog converter (DAC), a startup circuit, a multiplexer and an output amplifier. The DAC converts audio data into a first signal and a second signal. The startup circuit gradually increases a level of a startup voltage according to a reference voltage during a predetermined period. The multiplexer outputs the startup voltage as a control voltage during the predetermined period, and switches to output the reference voltage as the control voltage after the predetermined period has elapsed. The output amplifier generates an audio signal according to the control voltage, the first signal and the second signal. The control voltage is used to set a common mode voltage of the output amplifier.

Abstract: The transmitter includes a serializer, a main driver and an auxiliary driver. The serializer sequentially outputs, according to a clock signal, a first signal and a second signal as two consecutive data of a first output signal, and detects whether the first signal and the second signal are the same so as to generate a control signal. The main driver generates a second output signal according to the first output signal. The auxiliary driver is selectively switched according to the control signal, wherein the main driver and the auxiliary driver are powered by the same supply voltage.

Abstract: A low-dropout regulator includes a voltage divider circuit, an operation amplifier, a regulator circuit and an output circuit. The voltage divider circuit divides a power supply voltage to generate a predetermined voltage. The operational amplifier generates a bias voltage according to the predetermined voltage and an output voltage of an output terminal. The regulator circuit generates a first regulated voltage and a second regulated voltage according to the bias voltage. The output circuit adjusts a difference between a first current and a second current according to the first regulated voltage and the second regulated voltage to regulate the output voltage.

Abstract: The present invention discloses a video processing circuit, which is coupled to a memory chip and includes an image processing circuit. The image processing circuit includes a first channel, a second channel and a compression circuit. The two channels process first image data and second image data to generate first processed image data and second processed image data, respectively. The compression circuit compresses the first processed image data and the second processed image data to generate first compressed image data and second compressed image data, respectively. A memory block in the memory chip is configured as a ring buffer shared by the first channel and the second channel so as to store the first compressed image data and the second compressed image data.

Abstract: An intelligent processing device includes a first memory, a second memory, a memory management circuit and a convolution operation circuit. The memory management circuit transfers an input data from an external memory to the first memory. The convolution operation circuit reads the input data from the first memory, and performs multiple stages of calculations to generate multiple sets of feature map data. After a first data tile of a first feature map data is generated, the memory management circuit stores the first data tile to the second memory. When a data amount of the first data tile stored satisfies a predetermined value, the memory management circuit transfers the first data tile from the second memory to the first memory, and the convolution operation circuit reads the first data tile from the first memory and accordingly performs a second-stage calculation to generate a second data tile of a second feature map data.

Abstract: A still frame image decoding method includes: decoding a first frame in first data of multiple data according to a reference frame at a reference location of a memory, and storing the first frame to the reference location to overwrite at least one part of the reference frame; selecting the first data from the multiple data and decoding a second frame in the first data according to the first frame at the reference location in response to a still frame command; adjusting the second frame, and storing the adjusted second frame to an output location of the memory; preserving the first frame at the reference location; and again decoding the second frame according to the first frame at the reference location according to an end command, so as to store the second frame to the reference location to overwrite at least one part of the first frame.

Abstract: A post driver includes an input pair circuit, a protection circuit, a common mode sensing circuit and an amplifier. The input pair circuit outputs a first signal through a first node and outputs a second signal through a second node according to a first input signal and a second input signal. The protection circuit provides the input pair circuit with voltage protection according to multiple first bias voltages and a second bias voltage, transmits the first signal to a first load to generate a first output signal, and transmits the second signal to a second load to generate a second output signal. The common mode sensing circuit senses a level of the first node and a level of the second node to generate a feedback signal. The amplifier generates the second bias voltage according to a reference signal and the feedback signal.

Abstract: An image processing device includes a three-dimensional noise reduction (3D NR) circuit, an artificial intelligence noise reduction (AI NR) circuit, a weight determination circuit and an image blending circuit. The 3D NR circuit performs a 3D NR operation on input image data to generate first image data. The AI NR circuit performs an AI NR operation on the input image data to generate second image data. The weight determination circuit outputs a blending weight according to a motion index. The image blending circuit blends the first image data and the second image data according to the blending weight to generate output image data.

Abstract: The present invention discloses a neural network optimization method. An operator to be replaced is selected from multiple operators in a network layer according to a predetermined condition, and the operator to be replaced is replaced by multiple equivalent operators according to a calculation function corresponding to the operator to be replaced, wherein the multiple equivalent operators include a target operator. Pre-calculating is performed for a first operator among the multiple equivalent operators, and the calculation result is inputted into the target operator. A second operator is identified according to data change conditions of the multiple equivalent operators, and the second operator is combined with the target operator to complete optimization of a neural network model. The present invention can further perform lossless conversion of the operators in the neural network, further improving calculation performance on the basis of a simplified network structure.

Abstract: The present invention discloses a processor control method including: controlling a processor to execute a first operating system in a first state; when the processor executing the first operating system satisfies a predetermined condition, controlling the processor to switch from the first state to a second state; and controlling the processor to execute a second operating system in the second state, wherein an authority of the first state is higher than an authority of the second state.

Abstract: A data transmission control device is provided. The data transmission control device is disposed in a chip that includes a Peripheral Component Interconnect Express (PCIe) interface, and the data transmission control device is coupled to a memory that includes a block. The data transmission control device includes: a control circuit, a PCIe interface controller, and an address monitoring circuit. The PCIe interface controller is configured to receive a data. The address monitoring circuit is configured to issue an interrupt to the control circuit when the data is written to the block.

Abstract: An image processing device performs a filtering operation on image data according to a set of filter data, and includes a data reconstruction circuit, a memory and an intelligent processor. The data reconstruction circuit reconstructs data of blocks in the image data to generate first reconstruction data, and reconstructs the set of filter data to generate second reconstruction data. The memory stores the first reconstruction data and the second reconstruction data. The intelligent processor executes a depthwise convolution operation according to the first reconstruction data and the second reconstruction data to generate feature map data. Two adjacent of the multiple blocks have partially same data, and quantities of columns in the second reconstruction data are associated with a channel count of the depthwise convolution operation.

Abstract: An intelligent processor includes a first operation unit and a second operation unit. The first operation unit acquires first input data corresponding to a first operator, divides the first input data into multiple sets of first sub input data, and operates the first operator to perform an operation on the first sub input data to obtain first sub output data corresponding to each set of first input data. The second operation unit uses the first sub output data as second input data of the second operator, and operates the second operator to perform an operation on the second input data to obtain second output data corresponding to each set of second input data. Thus, the second operator need not wait until the first operator finishes all operations of the first input data, allowing two adjacent operator to achieve partial parallel calculation and improving operation efficiency.

Abstract: The present disclosure provides an image processing circuit including a neural network processor, a background processing circuit and a blending circuit. The neural network processor is configured to process input image data to determine whether the input image data has a predetermined object so as to generate to heat map. The background processing circuit blurs the input image data to generate blurred image data. The blending circuit blends the input image data and the blurred image data according to the heat map to generate output image data.

Abstract: An image processing method includes the following steps: performing first guided filtering on a target data to generate a first base layer data; generating a first detail layer data according to the target data and the first base layer data; performing second guided filtering on the first base layer data to generate a second base layer data; generating a second detail layer data according to the first base layer data and the second base layer data; converting the target data, the first base layer data or the second base layer data to obtain a converted base layer data; converting the first detail layer data and the second detail layer data to respectively generate a first converted detail layer data and a second converted detail layer data; and adding the converted base layer data and the first and second converted detail layer data to obtain an output data.

Abstract: A voltage mode transmitter circuit includes a low-dropout (LDO) regulator and an output circuit. The LDO regulator generates a driving voltage. The output circuit generates an output signal, and includes: a termination resistor, transmitting the output signal; a data processing circuit, driven by the driving voltage and adjusting a level of a node according to first and second data signals; a pre-emphasis circuit, transmitting a supply voltage to the node according to a control signal to adjust a transition edge of the output signal; a voltage protection circuit, providing an overvoltage protection according to a bias voltage, and coupling the node to the termination resistor. The data processing circuit, the pre-emphasis circuit, and the voltage protection circuit include at least one transistor, and a highest level of the output signal is higher than a withstand voltage of the at least one transistor.

Abstract: An audio processing apparatus having an echo canceling mechanism is provided. An audio transmission circuit receives an input digital audio signal from an external device. A DAC circuit performs conversion according to the input digital audio signal to generate an output analog audio signal to an external display device for power amplification and playback. An ADC circuit performs analog-to-digital conversion on an amplified signal generated by a power amplification circuit and a received audio signal generated by an audio receiving device to generate an amplified digital signal and a received digital audio signal. A processor implements an echo canceling algorithm to perform echo cancellation according to the amplified digital signal and the received digital audio signal to generate an output digital audio signal to be transmitted to the external device through the audio transmission circuit.

Abstract: A video data processing apparatus provided according to one embodiment of the present invention includes a processor and a blending circuit. The processor provides a first set of parameters according to a first channel identification signal and a second set of parameters according to a second channel identification signal. The blending circuit blends a first image into first video data at a first timing according to the first set of parameters and a second image into second video data at a second timing according to the second set of parameters. A time difference between the first timing and the second timing is less than a frame period of the first video data.