Abstract: An image processing chip is coupled to an external memory and includes a processing circuit and an encoder. The processing circuit is configured to write data to be encoded into a memory address of the external memory. The encoder includes first and second registers, a data input circuit, and an encoding circuit. The first register is configured to store the memory address under control of the processing circuit. The data input circuit is configured to read the data to be encoded from the external memory according to the memory address in the first register and write the data to be encoded into the second register. The encoding circuit is configured to perform an encoding operation according to the data to be encoded in the second register to generate encoded data. The encoder stores the encoded data or an output data derived from the encoded data in the external memory.

Abstract: A task processing system includes an intelligence processing unit and an instruction processor. The instruction processor receives a task originated from a main processor and enables the intelligence processing unit in response to the task. The intelligence processing unit selects a corresponding firmware file from a plurality of firmware files according to the task and re-enables the instruction processor, such that the instruction processor operates the corresponding firmware file and cooperates with the instruction processor to complete the task.

Abstract: A video encoding method for encoding a video including multiple frames, each containing multiple blocks, includes the following steps: reading multiple first characteristic data of a first frame from an external memory to a memory; reading multiple pixel data of a second frame from the external memory to the memory, the second frame being subsequent to the first frame; generating multiple second characteristic data of the second frame based on the pixel data in the memory; encoding, block by block, the pixel data of the second frame in the memory; calculating, block by block, a difference value between the first characteristic data and the second characteristic data; calculating motion information according to the difference values of the blocks; and determining an encoding bitrate based on the motion information.

Abstract: The present application discloses a memory allocation method, including: determining a plurality of target calculation models that need memory allocation; determining a target tensor of each of the target calculation models which a memory occupancy is needed during a calculation process; determining, according to lifecycles of the target tensors, a target memory space occupied by each of the target calculation models during the calculation process; and determining, according to the target memory spaces occupied by the target calculation models, a total memory space occupied by the target calculation models. Thus, an electronic apparatus is not required to allocate memory spaces for all the tensors, achieving the object of reducing the memory space occupied by calculation models.

Abstract: A video decoding method is applied to a decoder device to decode an encoded stream stored in memory. The decoder device includes a video decoder, a memory controller and a processor. The video decoding method includes: setting, by the memory controller, a decoded picture buffer in the memory according to a maximum number X of reference frames in the encoded stream, wherein the decoded picture buffer includes X+1 picture buffer areas, each picture buffer area is configured to store a decoded image, and X is a positive integer; determining an idle picture buffer area in the decoded picture according to status information of the decoded picture buffer; and controlling the video decoder to decode a current frame in the encoded stream to obtain a decoded image of the current frame and storing the decoded image of the current frame to the idle picture buffer area.

Abstract: A voltage detection method includes: outputting a corresponding one of voltages to be an input voltage according to a clock signal, a first detection signal, a reset signal and multiple first bits; generating the reset signal according to the clock signal and multiple currents, wherein the voltages and the currents are generated based on a power supply voltage; comparing the input voltage with a reference voltage to generate a second detection signal, and generating the first detection signal according to the second detection signal and an enable signal; and adjusting the first bits by a digital circuit according to the second detection signal during a trimming phase to determine the first bits, and outputting the first bits by the digital circuit and resetting the digital circuit according to the first detection signal during a voltage detection phase.

Abstract: A data padding device includes an internal memory, a direct memory access (DMA) circuit and a data processing circuit. The DMA circuit performs, according to a first padding control signal, data padding in a first direction on raw data during a process of reading the raw data from an external memory to generate first-direction padding data, and stores the first-direction padding data to the internal memory, wherein the first-direction padding data includes the raw data and first padding data originated from the raw data. The data processing circuit performs, according to a second padding control signal, data padding in a second direction on the first-direction padding data during a process of reading the first-direction padding data from the internal memory to generate second-direction padding data, wherein the second-direction padding data includes the first-direction padding data and second padding data originated from the first-direction padding data.

Abstract: An intrusion detection method includes steps of obtaining a current detection box and a historical detection box of a target in an input image; determining whether the current detection box has an intersection with a security line or a security area; determining that the target has an intrusion behavior if the current detection box has the intersection with the security line or the security area; and determining a direction of intrusion of the target according to the current detection box and the historical detection box.

Abstract: A sitting posture detection method includes: identifying an input image to generate a face frame under detection and a human frame under detection of a person under detection; calculating a plurality of face angles of the face frame under detection; calculating a plurality of bone feature point coordinates of the human frame under detection; and generating standard sitting posture data according to the face angles and the bone feature point coordinates, and determining a sitting posture of the person under detection according to the face angles, the bone feature point coordinates and the standard sitting posture data.

Abstract: A wired transceiver includes an output stage circuit and an input stage circuit. The output stage operates in one of a first mode and a second mode according to a mode control signal, and transmits multiple output signals to multiple output pads and receives a first set of bias voltages to provide a first overvoltage protection in the first mode, and stops transmitting the output signals and receives a second set of bias voltages to provide the overvoltage protection in the second mode. The input stage circuit receives multiple input signals from the output pads when the output stage circuit operates in the second mode, and attenuates the input signal to provide a second overvoltage protection.

Abstract: An image compression device includes a discrete cosine transform (DCT) circuit, a quantization noise shaping (QNS) circuit, and an encoder circuit. The DCT circuit performs a DCT on original image data to generate first data. The QNS circuit performs QNS on block data in first data to determine, based on a first coefficient and a second coefficient of the block data, a QNS score of the first coefficient, and replace the first coefficient with the second coefficient when the QNS score is greater than zero so as to generate second data, wherein the second coefficient is obtained by decreasing an absolute value of the first coefficient. The encoder circuit encodes the second data to generate compressed image data.

Abstract: A processing circuit performing a speech enhancement method processes a to-be-processed signal to generate a target signal and executes a plurality of program codes or program instructions to perform the following steps: performing Fourier transform on the to-be-processed signal to generate a spectral signal of the to-be-processed signal; performing a first noise reduction processing on the spectral signal to obtain a first intermediate signal; performing a noise analysis on the first intermediate signal to obtain a noise feature; performing a second noise reduction processing on the first intermediate signal to generate a second intermediate signal when the noise feature does not satisfy a target condition; and performing inverse Fourier transform on the second intermediate signal to generate the target signal. The first noise reduction processing is different from the second noise reduction processing.

Abstract: A fail-safe input/output device includes an input/output circuit, a comparator circuit and a resistance adjustment circuit. The input/output circuit transmits a voltage having a higher voltage level in a first supply voltage and a second supply voltage to a first node to generate a driving voltage, wherein a first target level of the first supply voltage is lower than a second target level of the second supply voltage. The comparator circuit compares the first supply voltage with the second supply voltage to generate a control signal, and selectively transmits the first supply voltage to the first node according to the control signal. The resistance adjustment circuit adjusts a resistance between the first node and a second node according to the second supply voltage, wherein the input/output circuit transmits the second supply voltage to the first node via the second node.

Abstract: A wired transmitter includes a digital-to-analog converter (DAC) and a line driver. The DAC generates first output signals according to a digital code, wherein a first circuit in the DAC operates in a first voltage domain and a second circuit of the DAC operates in a second voltage domain, and an upper limit of the first voltage domain is lower than an upper limit of the second voltage domain. The line driver operates in the second voltage domain, and generates second output signals according to the first output signals. Each of the DAC and the line driver is implemented by transistors corresponding to the first voltage domain.

Abstract: A video coding method includes the following steps: performing a first optimization operation on a sub-coding block to select original pixels or reconstructed pixels of an adjacent block of the sub-coding block according to a base prediction mode to generate an intermediate prediction mode of the sub-coding block; performing a second optimization operation on the sub-coding block to determine a prediction mode according to the intermediate prediction mode, the original pixels of the sub-coding block, and the reconstructed pixels of the adjacent block; generating prediction information of the sub-coding block according to the original pixels of the sub-coding block, the reconstructed pixels of the adjacent block, and the prediction mode; generating encoding coefficients and reconstructed pixels of the sub-coding block according to the prediction information of the sub-coding block; and generating a bit stream according to the encoding coefficients and the prediction information.

Abstract: A determination method for a chroma intra prediction mode includes: performing a simple RDO calculation on a luminance value of each pixel of an image block to obtain multiple luminance candidate modes; determining multiple chroma candidate modes according to one of the luminance candidate modes and a chroma simple RDO result calculated by performing a simple RDO calculation on a chroma value of each pixel of the image block; performing a full RDO calculation of the multiple luminance candidate modes on the luminance value of each pixel in the image block to select a luminance target mode; performing a full RDO calculation of the multiple chroma candidate modes on the chroma value of each pixel of the image block to a obtain chroma full RDO result; and determining a chroma target mode according to the luminance target mode and the chroma full RDO result.

Abstract: An electronic device includes a first and second decoding circuits and is coupled to a storage device and a memory, and the storage device stores compressed data. An operation method of the electronic device includes the following steps: performing a first read operation to read a first sub-block from a first read address of the storage device; performing a first write operation to write the first sub-block to a first write address of the memory; performing a second read operation to read a second sub-block from a second read address of the storage device; performing a second write operation to write the second sub-block to a second write address of the memory; reading via the first decoding circuit the first sub-block from the memory and decoding via the first decoding circuit the first sub-block; and reading via the second decoding circuit the second sub-block from the memory and decoding via the second decoding circuit the second sub-block.

Abstract: An operation method of a direct memory access (DMA) circuit comprising a buffer circuit and two channels includes following steps: determining first and second start addresses from the buffer circuit respectively according to first and second read requests of first and second channels that respectively correspond to first and second data; determining a read address according to the first start address and a read count; reading a first part of the first data from the buffer circuit according to the read address and updating the read count; reading at least one part of the second data from the buffer circuit according to the second start address after reading the first part of the first data; updating the read address according to the first start address and the updated read count; and reading a second part of the first data from the buffer circuit according to the updated read address.

Abstract: A voltage detection device includes a voltage divider circuit, a comparator circuit and a switch control circuit. The voltage divider circuit operates in a first mode based on a switching signal and divides a power voltage to generate an input voltage. The comparator circuit compares the input voltage with a set of reference voltages to generate a detection signal. The switch control circuit selectively adjusts a switching signal according to the detection signal after a predetermined period has elapsed from power-on of the power voltage so as to control the voltage divider circuit to switch from operating in the first mode to operating in a second mode. The first mode corresponds to a first target level of the power voltage, the second mode corresponds to a second target level of the power voltage, and the first target level is higher than the second target level.

Abstract: A memory management device includes a pre-fetch circuit, a setting circuit and a mapping circuit. The pre-fetch circuit acquires original data via a direct memory access (DMA) circuit, wherein the original data indicates a mapping relation between a first virtual address and multiple physical addresses. The setting circuit analyzes the original data to sequentially map the physical addresses to multiple second virtual addresses including the first virtual address and issues a write request. The mapping circuit stores a mapping relation between the physical addresses and the second virtual addresses as a first mapping table according the write request, and utilizes the first mapping table according to at least one read request corresponding to at least one channel of the DMA circuit to access the memory.