Abstract: An analog to digital converter (ADC) is disclosed having a coarse converter to generate the most significant bits of the output and double folding interpolation circuitry to generate the least significant bits. Each side of the double folding circuit includes additional folding stages coupled to reference voltages above and below the full scale input range of the ADC to cancel offset errors and improve circuit linearity. The interpolation circuit includes one interpolation stage, having two multiplier networks, for each least significant bit. Each interpolation stage receives two pairs of signals from the preceding stage and outputs two pairs of signals to the next stage. One of the pairs of output signals from each interpolation stage is also sent to a latched comparator. The outputs of all of the latched comparators can be read directly as the ADC output bits without requiring a decoder.

Abstract: A parallel analog-to-digital converter having comparators in a sequence with two sets of logic gates having inputs electrically connected to selected primary and complementary outputs of the comparators.

Abstract: A converter, of the type having an R-2R resistive network and switches, is used to convert a digital signal of n-bits into an analog signal. A plurality of first interconnectors is used to electrically connect a first switch input of one of the switches to a first voltage reference node by separately extending directly therebetween. A plurality of second interconnectors is used to electrically connect a second switch input on the same one of the switches to a second voltage reference node is a similar fashion.