Patents Assigned to Silex Microsystems AB
  • Patent number: 9620390
    Abstract: A wafer level method of making a micro-electronic and/or micro-mechanic device, having a capping with electrical wafer through connections (vias), comprising the steps of providing a first wafer of a semiconductor material having a first and a second side and a plurality of holes and/or recesses in the first side, and a barrier structure extending over the wafer on the second side, said barrier comprising an inner layer an insulating material, such as oxide, and an outer layer of another material. Then, metal is applied in said holes so as to cover the walls in the holes and the bottom of the holes. The barrier structure is removed and contacts are provided to the wafer through connections on the back-side of the wafer. Bonding structures are provided on either of said first side or the second side of the wafer. The wafer is bonded to another wafer carrying electronic and micro-electronic/mechanic components, such that the first wafer forms a capping structure covering the second wafer.
    Type: Grant
    Filed: January 12, 2016
    Date of Patent: April 11, 2017
    Assignee: Silex Microsystems AB
    Inventors: Thorbjorn Ebefors, Edvard Kalvesten, Tomas Bauer
  • Patent number: 9448401
    Abstract: A layered micro-electronic and/or micro-mechanic structure comprises at least three alternating electrically conductive layers with insulating layers between the conductive layers. There is also provided a via in a first outer layer, said via comprising an insulated conductive connection made of wafer native material through the layer, an electrically conductive plug extending through the other layers and into said via in the first outer layer in order to provide conductivity through the layers, and an insulating enclosure surrounding said conductive plug in at least one selected layer of said other layers for insulating said plug from the material in said selected layer. It also relates to micro-electronic and/or micro-mechanic device comprising a movable member provided above a cavity such that it is movable in at least one direction. The device has a layered structure according to the invention. Methods of making such a layered MEMS structure is also provided.
    Type: Grant
    Filed: November 6, 2013
    Date of Patent: September 20, 2016
    Assignee: Silex Microsystems AB
    Inventors: Thorbjorn Ebefors, Edvard Kalvesten, Peter Agren, Niklas Svedin
  • Patent number: 9362139
    Abstract: A wafer level method of making a micro-electronic and/or micro-mechanic device, having a capping with electrical wafer through connections (vias), comprising the steps of providing a first wafer of a semiconductor material having a first and a second side and a plurality of holes and/or recesses in the first side, and a barrier structure extending over the wafer on the second side, said barrier comprising an inner layer an insulating material, such as oxide, and an outer layer of another material. Then, metal is applied in said holes so as to cover the walls in the holes and the bottom of the holes. The barrier structure is removed and contacts are provided to the wafer through connections on the back-side of the wafer. Bonding structures are provided on either of said first side or the second side of the wafer. The wafer is bonded to another wafer carrying electronic and micro-electronic/mechanic components, such that the first wafer forms a capping structure covering the second wafer.
    Type: Grant
    Filed: November 19, 2009
    Date of Patent: June 7, 2016
    Assignee: Silex Microsystems AB
    Inventors: Thorbjörn Ebefors, Edvard Kälvesten, Tomas Bauer
  • Patent number: 9312217
    Abstract: The invention relates to a method of making a starting substrate wafer for semiconductor engineering having electrical wafer through connections (140; 192). It comprises providing a wafer (110; 150) having a front side and a back side and having a base of low resistivity silicon and a layer of high resistivity material on the front side. On the wafer there are islands of low resistivity material in the layer of high resistivity material. The islands are in contact with the silicon base material. Trenches are etched from the back side of the wafer but not all the way through the wafer to provide insulating enclosures defining the wafer through connections (140; 192). The trenches are filled with insulating material. Then the front side of the wafer is grinded to expose the insulating material to create the wafer through connections.
    Type: Grant
    Filed: January 31, 2007
    Date of Patent: April 12, 2016
    Assignee: Silex Microsystems AB
    Inventors: Edvard Kälvesten, Tomas Bauer, Thorbjörn Ebefors
  • Patent number: 8866289
    Abstract: A sealing and bonding material structure for joining semiconductor wafers having monolithically integrated components. The sealing and bonding material are provided in strips forming closed loops. There are provided at least two concentric sealing strips on one wafer. The strips are laid out so as to surround the component(s) on the wafers to be sealed off when wafers are bonded together. The material in the strips is a material bonding the semiconductor wafers together and sealing off the monolithically integrated components when subjected to force and optionally heating. A monolithically integrated electrical and/or mechanical and/or fluidic and/or optical device including a first substrate and a second substrate, bonded together with the sealing and bonding structure, and a method of providing a sealing and bonding material structure on at least one of two wafers and applying a force and optionally heat to the wafers to join them are described.
    Type: Grant
    Filed: January 5, 2012
    Date of Patent: October 21, 2014
    Assignee: Silex Microsystems AB
    Inventors: Thorbjorn Ebefors, Edward Kalvesten, Niklas Svedin, Anders Eriksson
  • Patent number: 8729685
    Abstract: A sealing and bonding material structure for joining semiconductor wafers having monolithically integrated components. The sealing and bonding material are provided in strips forming closed loops. There are provided at least two concentric sealing strips on one wafer. The strips are laid out so as to surround the component(s) on the wafers to be sealed off when wafers are bonded together. The material in the strips is a material bonding the semiconductor wafers together and sealing off the monolithically integrated components when subjected to force and optionally heating. A monolithically integrated electrical and/or mechanical and/or fluidic and/or optical device including a first substrate and a second substrate, bonded together with the sealing and bonding structure, and a method of providing a sealing and bonding material structure on at least one of two wafers and applying a force and optionally heat to the wafers to join them are described.
    Type: Grant
    Filed: April 30, 2010
    Date of Patent: May 20, 2014
    Assignee: Silex Microsystems AB
    Inventors: Thorbjörn Ebefors, Edward Kälvesten, Niklas Svedin, Anders Eriksson
  • Patent number: 8729713
    Abstract: A vent hole precursor structure (26) in an intermediate product for a semi-conductor device has delicate structures (27, 28), and said intermediate product has a cavity (21) with a pressure therein differing from the pressure of the surroundings. The intermediate product comprises a first wafer (20) in which there is formed a depression (21). The first wafer is bonded to a second wafer (22) comprising a device layer (23) from which the structures (27, 28) are to be made by etching. A hole or groove (26) having a predefined depth extends downwards into the device layer, such that the cavity (21) during etching is opened up before the etching procedure breaks through the device layer (23) to form the structures (27, 28).
    Type: Grant
    Filed: July 28, 2011
    Date of Patent: May 20, 2014
    Assignee: Silex Microsystems AB
    Inventors: Thorbjörn Ebefors, Edvard Kälvesten, Peter Agren, Niklas Svedin
  • Publication number: 20140063580
    Abstract: A layered micro-electronic and/or micro-mechanic structure comprises at least three alternating electrically conductive layers with insulating layers between the conductive layers. There is also provided a via in a first outer layer, said via comprising an insulated conductive connection made of wafer native material through the layer, an electrically conductive plug extending through the other layers and into said via in the first outer layer in order to provide conductivity through the layers, and an insulating enclosure surrounding said conductive plug in at least one selected layer of said other layers for insulating said plug from the material in said selected layer. It also relates to micro-electronic and/or micro- mechanic device comprising a movable member provided above a cavity such that it is movable in at least one direction. The device has a layered structure according to the invention. Methods of making such a layered MEMS structure is also provided.
    Type: Application
    Filed: November 6, 2013
    Publication date: March 6, 2014
    Applicant: SILEX Microsystems AB
    Inventors: Thorbjorn Ebefors, Edvard Kalvesten, Peter Agren, Niklas Svedin
  • Publication number: 20140042498
    Abstract: A substrate-through electrical connection (10) for connecting components on opposite sides of a substrate, and a method for making same. The connection includes a substrate-through via made from substrate material (10?). There is a trench (11) provided surrounding the via, the walls of the trench being coated with a layer of insulating material (12) and the trench (11) is filled with conductive or semi-conductive material (13). A doping region (15) for threshold voltage adjustment is provided in the via material in the surface of the inner trench wall between insulating material (12) and the material (10?) in the via. There are contacts (17?, 17?) to the via on opposite sides of the substrate, and a contact (18) to the conductive material (13) in the trench (11) so as to enable the application of a voltage to the conductive material (13).
    Type: Application
    Filed: April 19, 2012
    Publication date: February 13, 2014
    Applicant: SILEX Microsystems AB
    Inventor: Ulf Erlesand
  • Patent number: 8637351
    Abstract: The invention relates in a general aspect to a method of making vertically protruding elements on a substrate, said elements having a tip comprising at least one inclined surface and an elongated body portion extending between said substrate and said tip. The method comprises an anisotropic, crystal plane dependent etch forming said inclined surface(s); and an anisotropic, non crystal plane dependent etch forming said elongated body portion; combined with suitable patterning processes defining said protruding elements to have a predetermined base geometry.
    Type: Grant
    Filed: October 21, 2011
    Date of Patent: January 28, 2014
    Assignee: Silex Microsystem AB
    Inventors: Edvard Kälvesten, Thorbjörn Ebefors, Thierry Corman
  • Patent number: 8630033
    Abstract: A layered micro-electronic and/or micro-mechanic structure comprises at least three alternating electrically conductive layers with insulating layers between the conductive layers. There is also provided a via in a first outer layer, said via comprising an insulated conductive connection made of wafer native material through the layer, an electrically conductive plug extending through the other layers and into said via in the first outer layer in order to provide conductivity through the layers, and an insulating enclosure surrounding said conductive plug in at least one selected layer of said other layers for insulating said plug from the material in said selected layer. It also relates to micro-electronic and/or micro-mechanic device comprising a movable member provided above a cavity such that it is movable in at least one direction. The device has a layered structure according to the invention. Methods of making such a layered MEMS structure is also provided.
    Type: Grant
    Filed: June 22, 2011
    Date of Patent: January 14, 2014
    Assignee: Silex Microsystems AB
    Inventors: Thorbjörn Ebefors, Edvard Kälvesten, Peter Agren, Niklas Svedin, Thomas Ericson
  • Patent number: 8598676
    Abstract: A starting substrate in the form of a semiconductor wafer (1) has a first side and a second side, the sides being plane-parallel with respect to each other, and has a thickness rendering it suitable for processing without significant risk of being damaged, for the fabrication of combined analogue and digital designs, the wafer including at least two partitions (A1, A2; DIGITAL, ANALOGUE) electrically insulated from each other by insulating material (2; 38; 81; L) extending entirely through the wafer. A method for making such substrates including etching trenches in a wafer, and filling trenches with insulating material is also described.
    Type: Grant
    Filed: August 3, 2012
    Date of Patent: December 3, 2013
    Assignee: Silex Microsystems AB
    Inventors: Thorbjörn Ebefors, Tomas Bauer
  • Patent number: 8592981
    Abstract: The invention relates to a layered micro-electronic and/or micro-mechanic structure, comprising at least three alternating electrically conductive layers with insulating layers between the conductive layers. There is also provided a via in a first outer layer, said via comprising an insulated conductive connection made of wafer native material through the layer, an electrically conductive plug extending through the other layers and into said via in the first outer layer in order to provide conductivity through the layers, and an insulating enclosure surrounding said conductive plug in at least one selected layer of said other layers for insulating said plug from the material in said selected layer. It also relates to micro-electronic and/or micro-mechanic device comprising a movable member provided above a cavity such that it is movable in at least one direction. The device has a layered structure according to the invention. Methods of making such a layered MEMS structure is also provided.
    Type: Grant
    Filed: December 23, 2009
    Date of Patent: November 26, 2013
    Assignee: Silex Microsystems AB
    Inventors: Thorbjörn Ebefors, Edvard Kälvesten, Peter Ågren, Niklas Svedin
  • Patent number: 8485416
    Abstract: A sealing and bonding material structure for joining semiconductor wafers having monolithically integrated components. The sealing and bonding material are provided in strips forming closed loops. There are provided at least two concentric sealing strips on one wafer. The strips are laid out so as to surround the component(s) on the wafers to be sealed off when wafers are bonded together. The material in the strips is a material bonding the semiconductor wafers together and sealing off the monolithically integrated components when subjected to force and optionally heating. A monolithically integrated electrical and/or mechanical and/or fluidic and/or optical device including a first substrate and a second substrate, bonded together with the sealing and bonding structure, and a method of providing a sealing and bonding material structure on at least one of two wafers and applying a force and optionally heat to the wafers to join them are described.
    Type: Grant
    Filed: January 5, 2012
    Date of Patent: July 16, 2013
    Assignee: Silex Microsystems AB
    Inventors: Thorbjorn Ebefors, Edward Kalvesten, Niklas Svedin, Anders Eriksson
  • Patent number: 8324103
    Abstract: The invention relates to a method of providing a planar substrate with electrical through connections (vias). The method comprises providing a hole in said substrate and a treatment to render the substrate surface exhibiting a lower wettability than the walls inside the hole. The planar substrate is exposed to a molten material with low resistivity, whereby the molten material is drawn into the hole(s). It also relates to a semiconductor wafer as a starting substrate for electronic packaging applications, comprising low resistivity wafer through connections having closely spaced vias.
    Type: Grant
    Filed: January 31, 2007
    Date of Patent: December 4, 2012
    Assignee: Silex Microsystems AB
    Inventor: Tomas Bauer
  • Patent number: 8308960
    Abstract: The invention relates in a general aspect to a method of making vertically protruding elements on a substrate, said elements having a tip comprising at least one inclined surface and an elongated body portion extending between said substrate and said tip. The method comprises an anisotropic, crystal plane dependent etch forming said inclined surface(s); and an anisotropic, non crystal plane dependent etch forming said elongated body portion; combined with suitable patterning processes defining said protruding elements to have a predetermined base geometry.
    Type: Grant
    Filed: December 14, 2006
    Date of Patent: November 13, 2012
    Assignee: Silex Microsystems AB
    Inventors: Edvard Kälvesten, Thorbjörn Ebefors, Thierry Corman
  • Publication number: 20120267773
    Abstract: A wafer level method of making a micro-electronic and/or micro-mechanic device, having a capping with electrical wafer through connections (vias), comprising the steps of providing a first wafer of a semiconductor material having a first and a second side and a plurality of holes and/or recesses in the first side, and a barrier structure extending over the wafer on the second side, said barrier comprising an inner layer an insulating material, such as oxide, and an outer layer of another material. Then, metal is applied in said holes so as to cover the walls in the holes and the bottom of the holes. The barrier structure is removed and contacts are provided to the wafer through connections on the back-side of the wafer. Bonding structures are provided on either of said first side or the second side of the wafer. The wafer is bonded to another wafer carrying electronic and micro-electronic/mechanic components, such that the first wafer forms a capping structure covering the second wafer.
    Type: Application
    Filed: November 19, 2009
    Publication date: October 25, 2012
    Applicant: SILEX Microsystems AB
    Inventors: Thorbjörn Ebefors, Edvard Kälvesten, Tomas Bauer
  • Patent number: 7207227
    Abstract: In manufacturing a pressure sensor a recess that will form part of the sensor cavity is formed in a lower silicon substrate. An SOI-wafer having a monocrystalline silicon layer on top of a substrate is bonded to the lower silicon substrate closing the recess and forming the cavity. The supporting substrate of the SOI-wafer is then etched away, the portion of the monocrystalline layer located above the recess forming the sensor diaphragm. The oxide layer of the SOI-wafer here acts as an “ideal” etch stop in the case where the substrate wafer is removed by dry (plasma) or wet etching using e.g. KOH. This is due to high etch selectivity between silicon and oxide for some etch processes and it results in a diaphragm having a very accurately defined and uniform thickness. The cavity is evacuated by forming a opening to the cavity and then sealing the cavity by closing the opening using LPCVD. Sensor paths for sensing the deflection of the diaphragm are applied on the outer or inner surface of the diaphragm.
    Type: Grant
    Filed: October 17, 2005
    Date of Patent: April 24, 2007
    Assignee: Silex Microsystems AB
    Inventors: Pelle Rangsten, Edvard Kalvesten, Marianne Mechbach
  • Patent number: 7172911
    Abstract: A method of making a deflectable, free hanging micro structure having at least one hinge member, the method includes the steps of providing a first sacrificial wafer having a single crystalline material constituting material forming the micro structure. A second semiconductor wafer including necessary components for forming the structure in cooperation with the first wafer is provided. Finite areas of a structured bonding material is provided, on one or both of the wafers at selected locations, the finite areas defining points of connection for joining the wafers. The wafers are bonded using heat and optionally pressure. Sacrificial material is etched away from the sacrificial wafer, patterning the top wafer by lithography is performed to define the desired deflectable microstructures having hinges, and subsequently silicon etch to make the structures.
    Type: Grant
    Filed: February 14, 2003
    Date of Patent: February 6, 2007
    Assignee: Silex Microsystems AB
    Inventors: Edvard Kälvesten, Thorbjörn Ebefors, Niklas Svedin, H{dot over (a)}kan Westin
  • Patent number: 7017420
    Abstract: An entirely surface micromachined free hanging strain-gauge pressure sensor is disclosed. The sensing element consists of a 80 ?m long H-shaped double ended supported force transducing beam (16). The beam is located beneath and at one end attached to a square polysilicon diaphragm (14) and at the other end to the cavity edge. The sensor according to the invention enables a combination of high pressure sensitivity and miniature chip size as well as good environmental isolation. The pressure sensitivity for the sensor with a H-shaped force transducing beam, 0.4 ?m thick was found to be 5 ?V/V/mmHg.
    Type: Grant
    Filed: June 7, 2002
    Date of Patent: March 28, 2006
    Assignees: Silex Microsystems AB
    Inventors: Edvard Kälvesten, Patrik Melv{dot over (a)}s, Göran Stemme