Abstract: A method and apparatus for resolving priority among a plurality of data values. The priority resolution method of the invention analyzes the data values one bit at a time, starting from the most significant bit. In one embodiment, at an initial analysis step, the method determines whether the most significant bits of the data values are asserted. If at least one of the most significant bits is asserted, the data values that have unasserted most significant bits are eliminated from consideration. If none of the most significant bits is asserted, none of the data values will be eliminated at the initial step. The same analysis steps are repeated for each successive bit until only the largest data values remain. The priority resolution method of the present invention may be used to determine the smallest data value. In that embodiment, the data values are first bit-wise inverted.

Abstract: A range match circuit is disclosed for fast compare of an incoming address by partitioning the incoming address into fields. In one embodiment, a 16-bit incoming address is divided into quarterly fields, or four segments of 4-bit addresses, for comparison with a 16-bit top end boundary that has been divided into quarterly fields and a 16-bit bottom end boundary that has been divided into quarterly fields. Consequently, the range match circuit is able to analyze the entire 16-bit address field in parallel and perform simple combinational logic to determine if the incoming address is within the boundaries described by the top edge and bottom edge of the range.

Abstract: A 2T dual-port dynamic random access memory (DRAM) that can be fabricated using a pure logic process. Write/Refresh port is independent for any DRAM cell of the DRAM. Sense amplifier is built into each DRAM cell.

Abstract: A method and means to reduce memory requirements for storing statistics by recording, in a separate overflow memory, the most significant bits of counters requiring more bits than provided in the main statistics memory. A binary CAM provides the linking mechanism between the main and overflow memories.

Abstract: A static random access memory cell utilizes four NMOS transistors and does not require load elements. The semiconductor memory cell device maintains a stable data hold by utilizing a sub-threshold voltage to charge the word line, the sub-threshold voltage being higher than the low voltage reference of the memory cell device and lower than the threshold voltage of the NMOS access transistors. The sub-threshold voltage is biased to the word line during non-active and non-charging operations of the memory cell. The loadless four-transistor NMOS SRAM memory cell of the present invention requires a significantly smaller silicon area than prior art loadless four-transistor CMOS SRAM memory cells.

Abstract: A load-less 12-T TCAM wherein a TCAM cell uses two 1-bit 4-T SRAM storage cells that are scalable with technology. The TCAM has a TCAM cell that comprises two 1-bit 4-T SRAM data storage cells and a comparator. Within the TCAM cell, each of the two 1-bit 4-T SRAM storage cells is coupled to a BL by a pass-gate PMOS transistor that has a NP drain diode section. This NP drain diode section has a reverse-biased leakage current that is adapted to keep a dynamic node of the SRAM storage cell high without relying on any resistive-load element. The comparator is coupled to these two 1-bit 4-T SRAM storage cells. The comparator is adapted for matching a reference data with data communicated to the comparator from the two SRAM storage cells. The comparator is a 4-T comparator coupled to these two 4-T SRAM storage cells, thereby making the TCAM a 12-T load-less static TCAM.

Abstract: A content addressable memory (CAM) with built-in power saving management. The CAM includes a comparator circuit region that is coupled to a match line (ML) as well as a swing line (SL). The comparator circuit region is coupled to CAM cells. The comparator region is adapted for comparing match data with stored data within the CAM cells. The ML has its ML voltage level pre-charged to a pre-charge voltage level (Vc). Additionally, the SL is pre-charged to ground. In turn, in response to a data mismatch detected by the comparator, the ML voltage level drops from Vc by a ML voltage swing (Vswing) while the SL charge shares with the Ml. Advantageously, in response to this data mismatch, the SL charge shares with the ML such that Vswing is approximately less or equal to Vc/2. That is, the charge sharing prevents the ML from discharging all the way to ground.

Abstract: A ternary state content addressable memory (CAM) cell that includes two DRAM cells. In addition to a port for controlling and transmitting data to the CAM, another port is exclusively used for refreshing the DRAM cells. A refresh word line is coupled to the two DRAM cells for performing DRAW cell refresh. A refresh bit line is coupled to the first of the two DRAM cells for refreshing this first DRAM cell. A refresh bit line is coupled to the second of the two DRAM cells for refreshing this second DRAM cell. Problematic power consumption and voltage swing found in a conventional CAM are overcome in the CAM. A swing line (SL) is coupled to said first and second DRAM cells and a local match line (LML) of said CAM cell, said SL having an adjustable voltage level for changing voltage swing in said LML to regulate trade-off between power consumption and speed of said CAM cell.

Abstract: A memory architecture is disclosed that employs multiple column redundancies which provide multiple options for replacing a defective global odd or even bit line. Each column memory has two multiplexers, one for selecting a global odd bit line and another for selecting a global even bit line. Two or more column redundancies are coupled to each of the multiplexer in the column memory. In a first embodiment, the global odd and even bit lines are connected through odd and even sense amps in a regular column. In a second embodiment, the global odd bit line in a regular column connects through odd sense amps, while the global even bit line in the regular column connects through even sense amps. In a third embodiment, two or more sets of redundancy columns are commonly coupled to a left adjacent regular column and a right adjacent regular column.

Abstract: The invention discloses a low-power ternary CAM by utilizing four encoded comparand datalines, C0, C1, C2, and C3 in a twin ternary cell. The twin ternary cell is a composite of two ternary CAM bits. The two binary CAM bits are coded so that only one of four comparand datalines is toggled during a compare operation. The encoded data is stored and used for comparison. In one embodiment, the four possible states for the 2 bit comparands are coded as 0001, 0010, 0100, and 1000.

Abstract: The present invention discloses a parallel test circuit and method for testing even bit line and odd bit line in a memory block simultaneously. The parallel test circuit comprises an even test circuit for testing an even bit line and an odd test circuit for testing an odd bit line. The parallel test circuit also includes a write circuit for writing data to a bit line, a read circuit including a data sense amp, an output buffer, and a comparator. Furthermore, the present invention provides the capability to conduct disturbance test in neighboring even and odd cells.

Abstract: A system and/or method for simultaneous read/write access of 1-Transistor (1-T) dynamic random access memory (DRAM), which does not rely on a dual-port DRAM to perform read and write accesses within single clock cycle. A single-port 1-T DRAM works with modified design of read sense amplifier to perform both read and write accesses within single clock cycle, thereby retaining high performance and compact size that characterize the 1-T DRAM while allowing simultaneous read/write access that characterizes dual-port memory. Hence, single-port 1-T DRAM constitutes a pseudo dual-port 1-T DRAM that emulates the dual-port DRAM's ability in performing simultaneous read/write memory access of 1-T DRAM.

Abstract: A dynamic random access memory (DRAM) having a conventional cell layout and having its data access path adapted to access a ‘zero’ faster than a ‘one.’ The DRAM comprising two capacitors coupled respectively to two neighboring word lines. The two capacitors are also coupled respectively to two neighboring bit lines via two pass gates. Data is represented as complementary data bits on the two capacitors. In so doing, a ‘zero’ is ensured to be stored in either one of the two capacitors. A voltage level ‘zero’ is in turn ensured to be maintained on the bit line coupled to the capacitor that stores the ‘zero’ data bit. The sense amplifier and the write driver take advantage of the fact that a voltage level ‘zero’ is ensured to be maintained in either one of the two bit lines.