Abstract: A method and apparatus for resolving priority among a plurality of data values. The priority resolution method of the invention analyzes the data values one bit at a time, starting from the most significant bit. In one embodiment, at an initial analysis step, the method determines whether the most significant bits of the data values are asserted. If at least one of the most significant bits is asserted, the data values that have unasserted most significant bits are eliminated from consideration. If none of the most significant bits is asserted, none of the data values will be eliminated at the initial step. The same analysis steps are repeated for each successive bit until only the largest data values remain. The priority resolution method of the present invention may be used to determine the smallest data value. In that embodiment, the data values are first bit-wise inverted.

Abstract: A range match circuit is disclosed for fast compare of an incoming address by partitioning the incoming address into fields. In one embodiment, a 16-bit incoming address is divided into quarterly fields, or four segments of 4-bit addresses, for comparison with a 16-bit top end boundary that has been divided into quarterly fields and a 16-bit bottom end boundary that has been divided into quarterly fields. Consequently, the range match circuit is able to analyze the entire 16-bit address field in parallel and perform simple combinational logic to determine if the incoming address is within the boundaries described by the top edge and bottom edge of the range.

Abstract: A 2T dual-port dynamic random access memory (DRAM) that can be fabricated using a pure logic process. Write/Refresh port is independent for any DRAM cell of the DRAM. Sense amplifier is built into each DRAM cell.

Abstract: A method and means to reduce memory requirements for storing statistics by recording, in a separate overflow memory, the most significant bits of counters requiring more bits than provided in the main statistics memory. A binary CAM provides the linking mechanism between the main and overflow memories.

Abstract: A static random access memory cell utilizes four NMOS transistors and does not require load elements. The semiconductor memory cell device maintains a stable data hold by utilizing a sub-threshold voltage to charge the word line, the sub-threshold voltage being higher than the low voltage reference of the memory cell device and lower than the threshold voltage of the NMOS access transistors. The sub-threshold voltage is biased to the word line during non-active and non-charging operations of the memory cell. The loadless four-transistor NMOS SRAM memory cell of the present invention requires a significantly smaller silicon area than prior art loadless four-transistor CMOS SRAM memory cells.

Abstract: A load-less 12-T TCAM wherein a TCAM cell uses two 1-bit 4-T SRAM storage cells that are scalable with technology. The TCAM has a TCAM cell that comprises two 1-bit 4-T SRAM data storage cells and a comparator. Within the TCAM cell, each of the two 1-bit 4-T SRAM storage cells is coupled to a BL by a pass-gate PMOS transistor that has a NP drain diode section. This NP drain diode section has a reverse-biased leakage current that is adapted to keep a dynamic node of the SRAM storage cell high without relying on any resistive-load element. The comparator is coupled to these two 1-bit 4-T SRAM storage cells. The comparator is adapted for matching a reference data with data communicated to the comparator from the two SRAM storage cells. The comparator is a 4-T comparator coupled to these two 4-T SRAM storage cells, thereby making the TCAM a 12-T load-less static TCAM.