Abstract: A memory chip having a system for controlling sensing time of a data sense amplifier (DSA). A global control is adapted for initiating data access to the memory blocks. A wire path coupling the global control to each memory block is utilized by each memory block as a part of transmitting path for receiving a block enable signal sent from the global control. Specifically, a memory block includes a wired-NOR circuit adapted to send a DSA enable signal to the DSA in response to being selected by a block enable signal. In contrast to a simple delay circuit that only controls the DSA roughly, this wired-NOR circuit tracks internal read signal, and controls the DSA tightly. The time from the activation of the block enable signal by the global control to the enabling of the DSA stays approximately the same irrespective of the memory block's location in the memory chip. Block location independence of DSA sensing time allows tighter memory cycle.

Abstract: DRAM with column slices improves circuit redundancy. Slices have global column length, and memory is divided in groups with size of redundancy columns having slices. Failure detected among slices of corresponding storage is replaced by corresponding redundancy column slice, such that column redundancy division is in vertical column direction. Column includes global data line shared by column slices and multiple blocks. Redundant column is added to memory array, and redundant control circuits or comparator are proximate to data sense amplifiers. Defective column address are provided to controller through non-volatile memory, or laser-blown or electrically-programmable fuses. When column address is presented, incoming address is compared with stored address, such that select data is output on redundant data line when equal addresses (i.e., hit detect), or normal data is output when unequal addresses (i.e., "miss" detected).