Abstract: This invention pertains to multicarrier systems where the Peak power to Average power Ratio (PAR) is generally high, and where the system has a Forward Error Correction (FEC) mechanism. A peak detection mechanism, a procedure for choosing a subcarrier to be modified and a symbol modifier scheme are disclosed for lowering the peak power of a signal while minimizing coding errors. The peak detector uses a threshold for determining whether the PAR reduction is to be applied. A subcarrier symbol(s) to be modified is identified depending on the number of peaks in a frame, by determining the subcarrier symbol which has the maximum effect on the peaks in the frame. One method chooses the subcarrier with the greatest overall effect on a peak in the frame, a second method selects the subcarrier that gives the minimum sum of residual peaks, and a third method is limited to situations where there are only two peaks.

Abstract: A memory architecture is provided to enable parallel access along any dimension of an n-dimensional data array. To enable parallel access of s data elements along any dimension, the data elements of n-dimensional data array are mapped to s parallel memory banks in such a way that consecutive s data elements along any dimension are mapped to different memory banks. This mapping is defined by two functions, which define the memory bank number and location within a memory bank for each data element in n-dimensional data array. The necessary and sufficient conditions, which the mapping functions should satisfy in order to enable parallel data access, are described. These generic function pairs are described for all combinations of (n, s). Two particular instances of the mapping, namely circular permutation (rotation) along 0th dimension and dyadic permutation along 0th dimension have been discussed in detail.

Abstract: A method and apparatus is provided that computes an optimal estimate of known clock frequency error between the transmitter and receiver using a known pilot signal and the statistics of the noise process. The estimate is computed such that the residual clock error is below the least count (the smallest frequency correction that can be imparted) of the VCXO that controls the receiver sample clock. A tracking technique based on a measure of drift in taps of frequency domain equalizers of different sub-carriers is disclosed. This tracking ensures that the residual mean square error is within a predefined bound. Finally, the least count effects in digitally controlled oscillators (DAC controlled VCXOs and Numerically Controlled Oscillators (NCXO)) are addressed by a dithering mechanism. The dithering mechanism involves imparting positive and negative clock corrections for different lengths of time in such a manner that the residual clock error becomes zero mean.