Abstract: Disclosed are an interconnection module substrate for a semiconductor package, a semiconductor package device including the same, and manufacturing methods thereof. The interconnection module substrate includes a plurality of via-defining structures disposed spaced apart from each other in a horizontal direction, each of the plurality of via-defining structures including a substrate material unit and a conductive via element extending through the substrate material unit in a vertical direction, at least one interconnection bridge member disposed spaced apart from or adjacent to the plurality of via-defining structures in the horizontal direction, and a substrate material layer embedded in the space between and around the plurality of via-defining structures and the interconnection bridge member to form a single substrate shape together therewith, the substrate material layer being configured to expose the plurality of via-defining structures and the interconnection bridge member.

Abstract: Disclosed is a method of manufacturing a fan-out packaging device, which is a method of manufacturing a packaging device using a wafer or panel level packaging process, the method including forming a first dielectric layer having a first via hole on a fan-out packaging substrate, forming a redistribution layer (RDL) on the first dielectric layer and the first via hole, forming a second dielectric layer having a second via hole formed on the redistribution layer, and forming a bump structure on the second dielectric layer and the second via hole so as to be connected to the redistribution layer, wherein the redistribution layer includes a metal sealing ring to extend a conductor path in a plating process.

Abstract: Disclosed is a method of manufacturing a fan-out packaging device, which is a method of manufacturing a packaging device using a wafer or panel level packaging process, the method including forming an additional GND layer on a part of a fan-out packaging substrate, forming a first dielectric layer having a first via hole on the additional GND layer, forming a redistribution layer (RDL) on the first dielectric layer and the first via hole, forming a second dielectric layer having a second via hole on the redistribution layer, and forming a bump structure on the second dielectric layer and the second via hole so as to be connected to the redistribution layer, wherein the additional GND layer is formed in directions toward four sides or at least two opposite sides of a die.

Abstract: Disclosed is a fan-out package in which two or more dies are integrated in a fan-out packaging process, wherein the fan-out package includes a bridge structure including a bridge substrate formed on one side of the fan-out package, a redistribution layer formed on the bridge substrate, the redistribution layer including at least one trace, the redistribution layer being configured to electrically connect the dies to each other, and a passive element formed in the redistribution layer by patterning. The routing density of the trace is relieved, and electrical performance is improved by the provision of the passive element.

Abstract: Disclosed is a method of manufacturing a fan-out packaging device using wafer or panel level packaging including forming a temporary adhesive layer on a carrier substrate, attaching a die to the temporary adhesive layer, attaching a preformer, molding the die and the preformer on the temporary adhesive layer, separating the fan-out packaging substrate from the carrier substrate and the temporary adhesive layer, forming a temporary protective layer, forming a rear metal layer connected to the metal via, and removing the temporary protective layer and then forming a re-distribution line structure, and a bump structure connected to the re-distribution line structure.

Abstract: Disclosed is a method of manufacturing a fan-out packaging device using wafer or panel level packaging including forming a base metal layer on a partial area of a fan-out packaging substrate, forming a first dielectric layer on the base metal layer, patterning the first dielectric layer to form a via hole, forming a redistribution layer (RDL) on the first dielectric layer and the via hole, forming a second dielectric layer on the redistribution layer (RDL), and patterning the second dielectric layer to form a bump structure connected to the redistribution layer.