Patents Assigned to Silicon Design Systems Ltd.
  • Methods and apparatus for validating design changes without propagating the changes throughout the design
    Patent number: 7516431
    Abstract: Methods and apparatus for validating design changes in an integrated circuit design without propagating the effects of individual design changes to every location in the integrated circuit design. Local sensitivity functions at design nodes are aggregated and merged at interconnecting nodes in a recursive process.
    Type: Grant
    Filed: April 11, 2006
    Date of Patent: April 7, 2009
    Assignee: Silicon Design Systems Ltd.
    Inventors: Yzhar Keysar, Anatoli Shindler, Yuri Miroshnik
  • Integrated circuit (IC) having IC floorplan silhouette-like power supply net, and sea of supply (SoS) electronic design automation (EDA) tool for designing same
    Patent number: 7346884
    Abstract: An integrated circuit (IC) having an IC floorplan silhouette-like power supply net, and a computer executable Sea of Supply (SoS) Electronic Design Automation (EDA) tool for automatically designing same. An IC floorplan silhouette-like power supply net preferably includes both a Sea-of-Supply (SoS) power net and a Sea-of-Supply (SoS) ground net each exclusively occupying different layers of the two lowermost metal layers of an interconnect structure overlying its underlying transistor embedded silicon based structure. The SoS nets are the logical complement of preferably all the exempt areas of an IC floorplan.
    Type: Grant
    Filed: September 13, 2005
    Date of Patent: March 18, 2008
    Assignee: Silicon Design Systems Ltd.
    Inventors: Yuri Miroshnik, Anatoli Shindler, Svetlana Yurin
  • Integrated circuit (IC) having IC floorplan silhouette-like power supply net, and sea of supply (SoS) electronic design automation (EDA) tool for designing same
    Patent number: 6957401
    Abstract: An integrated circuit (IC) having an IC floorplan silhouette-like power supply net, and a computer executable Sea of Supply (SoS) Electronic Design Automation (EDA) tool for automatically designing same. An IC floorplan silhouette-like power supply net preferably includes both a Sea-of-Supply (SoS) power net and a Sea-of-Supply (SoS) ground net each exclusively occupying different layers of the two lowermost metal layers of an interconnect structure overlying its underlying transistor embedded silicon based structure. The SoS nets are the logical complement of preferably all the exempt areas of an IC floorplan.
    Type: Grant
    Filed: April 1, 2003
    Date of Patent: October 18, 2005
    Assignee: Silicon Design Systems Ltd.
    Inventors: Yuri Miroshnik, Anatoli Shindler, Svetlana Yurin
  • Computerized standard cell library for designing integrated circuits (ICs) with high metal layer intra cell signal wiring, and ICs including same
    Patent number: 6892370
    Abstract: The present invention is for a computerized standard cell library with inter alia standard cells having high metal layer intra cell signal wiring for use in designing ICs in accordance with a standard cell IC design methodology. High metal layer intra cell signal wiring in accordance with the present invention arises to wire segments in an IC's high interconnect metal layer exclusively reserved for horizontal wire segments being constrained to a limited number of horizontal routing tracks, thereby leaving the remaining horizontal routing tracks unimpeded for inter cell signal wiring purposes.
    Type: Grant
    Filed: April 2, 2003
    Date of Patent: May 10, 2005
    Assignee: Silicon Design Systems Ltd.
    Inventor: Dorit Flohr