Abstract: A method and apparatus for creating a display list permitting multiple states of the same type for a single primitive. By introducing a plurality of state variables of the same type in a predetermined order in a display list before a primitive description, different state variables of the same type are applied to different vertex descriptors of the primitive. In one embodiment, the state variables introduced are starting addresses of the groups of vertices addressable by vertex indices of the primitive. In a case where the primitive is a triangle, up to three different starting addresses might be introduced into the display list (one corresponding to each vertex of the triangle). By introducing multiple starting addresses, the vertex indices of the triangle description can be significantly shortened, the concern about variable length inputs can be eliminated, and each index is independent of its predecessor in the master display list.

Abstract: A parallel speculative decoder is described. The decoder includes a set of partial decoders and an additional decoder. The partial decoders are aligned at different positions of a portion of an input data stream and speculatively and simultaneously decode symbols (e.g., codewords) having less bits than a longest symbol length. The additional decoder decodes symbols in the event the first partial decoder does not produce valid decoding results.

Abstract: A scalable, three-dimensional (3D) graphics subsystem. The graphics subsystem includes a plurality of graphics modules each including a rendering module and a dedicated memory. In one embodiment, the rendering modules of the graphics modules are coupled together, possibly through a routing device, such that each rendering module views the memory space, formed by all dedicated memory, as one continuous shared memory.

Abstract: A sense amplifier for sensing data from a pair of complementary bit lines. A bistable circuit is coupled to the bit lines through a pair of transistors. During the beginning of a sensing cycle, the transistors conduct allowing the bistable circuit to begin sensing the data on the lines. However, before the sense amplifier reaches one of its two stable states, the pair transistors cease conducting and isolate the bistable circuit from the bit lines. In this manner, the load associated with the bit lines is removed from the bistable circuit allowing it to more quickly sense data.

Abstract: An improved static memory is described which, when used in a dual port cache memory simplifies write cycles by providing latching of decoded address signals which are used in a subsequent memory cycle for writing. Improved logic is described which allows the propagation of data at the rate .function. with timing signals of frequency 1/2.function.. An improved sense amplifier which is isolated from the column lines is the array is used.