Abstract: A two-stage cascaded processor engine for Digital Signal Processing (DSP) utilizing parallel multi-port memories and a plurality of arithmetic units, including adders and multiplier-accumulators (MACs) is described. The engine supports a Single Instruction Multiple Data (SIMD) architecture. Conventional cascaded processors implementing an add-multiply-accumulate-add process for Short Length Transforms have significant limitations which are removed by the invention. The two stage processor uses two multiport memories. Arithmetic units (AU) in the top stage get their operands from a top multiport RAM and arithmetic units in the bottom stage get their operands from a bottom multiport RAM. AU outputs are stored back into the same stage as multiport RAM and passed either to the next stage or the output bus. The AU outputs can be both stored back into the same stages multiport RAM or passed either to the next stage or output multiplexer, or both of the previous.