Patents Assigned to SILICON FIDELITY, INC.
  • Patent number: 10367419
    Abstract: A switching regulator may comprise an inductor housed in an inductor housing, a wire electrically coupled to the inductor and housed in the inductor housing, an electrical component including a terminal, and a board including a board trace. The board trace may electrically couple the terminal with first wire. The electrical component and the inductor housing may be attached to the board. The attachment of the inductor housing to the board may create a space between the inductor housing and the board. The electrical component may be disposed within the space.
    Type: Grant
    Filed: August 29, 2018
    Date of Patent: July 30, 2019
    Assignees: Kinetic Technologies, Silicon Fidelity, Inc.
    Inventors: Farshid Iravani, Kin Shum, Jan Nilsson, William Robert Pelletier
  • Patent number: 10069417
    Abstract: A switching regulator may include an inductor housing, a board, and one or more electrical components. The inductor housing may house an inductor and one or more wires. The board may include one or more board traces and one or more solder pads. The electrical components may include one or more chips, capacitors, voltage sources, and/or other electrical components. The inductor housing may be attached to the board to create a space between the inductor housing and the board. The space may be created underneath the inductor housing and above the board. One or more electrical components may be attached to the board. One or more electrical components may be disposed within the space.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: September 4, 2018
    Assignees: Kinetic Technologies, Silicon Fidelity, Inc.
    Inventors: Farshid Iravani, Kin Shum, Jan Nilsson, William Robert Pelletier
  • Patent number: 9673319
    Abstract: A slotted gate power transistor is a lateral power device including a substrate, a gate dielectric formed over the substrate, a channel region in the substrate below the gate dielectric and gate electrode layer formed over the gate dielectric. The gate electrode layer overlaps the gate dielectric above the channel region, an accumulation region, and a drift region below an oxide filled shallow trench isolation (or STI) or locally oxidized silicon (LOCOS) region. The slotted gate power transistor includes one or more slots or openings on the gate electrode layer over the accumulation region. Electrical connectivity is maintained over the entire gate electrode layer without external wiring.
    Type: Grant
    Filed: March 10, 2016
    Date of Patent: June 6, 2017
    Assignees: KINETIC TECHNOLOGIES, SILICON FIDELITY, INC.
    Inventors: Farshid Iravani, Jan Nilsson