Abstract: A voltage reference circuit employs a bandgap cell to establish a voltage reference, stabilized relative to the bandgap voltage of silicon, and a compensation circuit for compensating non-linear temperature dependence of the bandgap stabilized voltage reference. A two or three transistor type bandgap cell may be employed to establish the bandgap reference voltage along with a voltage divider network to adjust the output reference voltage relative to the bandgap voltage of silicon. The compensation circuit preferably employs a compensation resistor in the resistor divider network, and a switching circuit for switching current therethrough. This provides empirically determined adjustments to the output reference voltage by switching current through the compensation resistor in accordance with predetermined temperature thresholds.

Abstract: A method for forming a dielectrically isolated semiconductor devices on a semiconductor substrate. An epitaxial layer is grown on a wafer having a thin buried oxide layer. Trench regions are etched through the epitaxial layer to the underlying oxide layer. A dielectric isolation layer is formed on the sidewalls of the trench regions so as to isolate an active region of the epitaxial semiconductor material. The trenches are etched to the underlying semiconductor substrate and the semiconductor material is selectively epitaxially regrown in the trench regions. Semiconductor devices are formed in the isolated active regions. Contacts are made to the active regions of the semiconductor device and to the wafer substrate through the epitaxially regrown trench regions.

Abstract: The circuitry of the present invention taps a DS0 data stream and outputs a timing signal to drive terminal multiplexers. Even if the data bit stream is lost, the present invention continues to provide proper clocking signals. A composite clock (bit and byte clock) is provided by the present invention with the bit clock at 64 KHz and the byte clock at 8 KHz in the preferred embodiment. To avoid the problem of phase shift over long distances (limiting cable length) the present invention phase adjusts the digital bit stream clocking signal with a 360 degree delay, giving the appearance of advancing the signal in phase. An additional delay of one frame width is applied to the signal. A negative phase delay equivalent to cable runs from 0-1500 feet in 500 foot increments is also applied. In the preferred embodiment, a shift register is tapped in reverse order to accomplish this phase delay.

Abstract: The present invention provides a clock holdover circuit which will provide a replacement clock signal within predetermined parameters independently of time and temperature variations. The circuit of the present invention has only a single component which is time and temperature dependent. By selecting the components parameters to be within the desired tolerances, the accuracy of the circuit is maintained. In the present invention, digital circuitry is combined with an accurate local crystal frequency source to provide a replacement clock signal. The present invention allows phase consistency upon loss of a reference clock signal as well as on return of the reference clock signal. A reference clock signal is phase locked to a VCO to produce a desired output. The frequency of the output is compared to a local frequency standard to generate an offset frequency used to control a frequency synthesizer. The offset frequency is digitally stored.

Abstract: A differential variable gain transconductance amplifier suitable for but not limited to applications requiring operation with a power supply of less than 1.0V. The circuit is suitable for fabrication by integrated circuit technology and is composed of three major blocks: an input stage, a current summing gain control stage, and an output stage. The differential input stage is comprised of two identical voltage-to-current converters, with one used as the positive input and the other as the negative input. The current summing stage uses the principal of summation of opposite but equal currents canceling to produce attenuated gain. The output stage converts current into voltage and produces a single ended output.

Abstract: A pulse width modulation comparator having internal latching and resetting functions. The comparator includes a differential input stage having first and second outputs which are connected to supply first and second transistors in a voltage gain stage, respectively. The first output of the input stage drives both of the transistors of the voltage gain stage. The second output of the input stage is connected to drive an output transistor as well as to supply the second transistor of the voltage gain stage. The output of the output transistor is connected via feedback circuitry to drive the transistors of the voltage gain stage. A shunt transistor forms part of the feedback circuit and serves to divert the feedback signal from the voltage gain stage transistors upon the application of a clock reset pulse.An analog voltage is applied to one input of the input stage and a ramp or triangular waveform is applied to the other input.

Abstract: A circuit design suitable for use with monolithic semiconductor fabrication techniques which provides two accurate reference voltages, one of which is a certain calculatable percentage greater than, the other of which is the same percentage less than, a fixed reference voltage. The magnitude of this voltage window is set by selection of the value of a single resistor which is connected between a single connection point in the circuit and ground. The two accurate reference voltages are fully compensated for changes in temperature.