Patents Assigned to SILICON GENESIS
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Patent number: 10087551Abstract: A method for slicing a crystalline material ingot includes providing a crystalline material boule characterized by a cropped structure including a first end-face, a second end-face, and a length along an axis in a first crystallographic direction extending from the first end-face to the second end-face. The method also includes cutting the crystalline material boule substantially through a first crystallographic plane in parallel to the axis to separate the crystalline material boule into a first portion with a first surface and a second portion with a second surface. The first surface and the second surface are planar surfaces substantially along the first crystallographic plane. The method further includes exposing either the first surface of the first portion or the second surface of the second portion, and performing a layer transfer process to form a crystalline material sheet from either the first surface of the first portion or from the second surface of the second portion.Type: GrantFiled: September 13, 2016Date of Patent: October 2, 2018Assignee: SILICON GENESIS CORPORATIONInventor: Francois J. Henley
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Patent number: 10049915Abstract: A stacked semiconductor device is formed by implanting ions through dielectric and conductive structures of a first substrate to define a cleave plane in the first substrate, cleaving the first substrate at the cleave plane to obtain a cleaved layer including the dielectric and conductive structures, bonding at least one die to the first substrate, the at least one die having a smaller width than a width of the first substrate, depositing a planarization material over the at least one die, planarizing the planarization material to form a planarized upper surface over the at least one die, and stacking a third substrate on the planarized upper surface.Type: GrantFiled: December 1, 2017Date of Patent: August 14, 2018Assignee: SILICON GENESIS CORPORATIONInventors: Theodore E. Fong, Michael I. Current
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Patent number: 9704835Abstract: A method comprises providing a first substrate having dielectric structures and conductive structures. Ions are implanted into the first substrate, the ions traveling through the dielectric structures and the conductive structures to define a cleave plane in the first substrate. The first substrate is cleaved at the cleave plane to obtain a cleaved layer having the dielectric structure and the conductive structures. The cleaved layer is used to form a three-dimensional integrated circuit device having a plurality of stacked integrated circuit (IC) layers, the cleaved layer being one of the stacked IC layers.Type: GrantFiled: January 11, 2016Date of Patent: July 11, 2017Assignee: SILICON GENESIS CORPORATIONInventors: Theodore E. Fong, Michael I. Current
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Patent number: 9362439Abstract: A film of material may be formed by providing a semiconductor substrate having a surface region and a cleave region located at a predetermined depth beneath the surface region. During a process of cleaving the film from the substrate, shear in the cleave region is carefully controlled. According to certain embodiments, an in-plane shear component (KII) is maintained near zero, sandwiched between a tensile region and a compressive region. In one embodiment, cleaving can be accomplished using a plate positioned over the substrate surface. The plate serves to constrain movement of the film during cleaving, and together with a localized thermal treatment reduces shear developed during the cleaving process. According to other embodiments, the KII component is purposefully maintained at a high level and serves to guide and drive fracture propagation through the cleave sequence.Type: GrantFiled: May 4, 2009Date of Patent: June 7, 2016Assignee: SILICON GENESIS CORPORATIONInventor: Francois J. Henley
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Patent number: 9356181Abstract: A thickness of material may be detached from a substrate along a cleave plane, utilizing a cleaving process controlled by a releasable constraint plate. In some embodiments this constraint plate may comprise a plate that can couple side forces (the “P-plate”) and a thin, softer compliant layer (the “S-layer”) situated between the P-plate and the substrate. In certain embodiments a porous surface within the releasable constraint plate and in contact to the substrate, allows the constraint plate to be secured to the substrate via a first pressure differential. Application of a combination of a second pressure differential within a pre-existing cleaved portion, and a linear force to a side of the releasable constraint plate bound to the substrate, generates loading that results in controlled cleaving along the cleave plane.Type: GrantFiled: February 10, 2015Date of Patent: May 31, 2016Assignee: SILICON GENESIS CORPORATIONInventors: Francois Henley, Al Lamm, Yi-Lei Chow
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Patent number: 9336989Abstract: Embodiments relate to use of a particle accelerator beam to form thin layers of material from a bulk substrate. In particular embodiments, a bulk substrate (e.g. donor substrate) having a top surface is exposed to a beam of accelerated particles. In certain embodiments, this bulk substrate may comprise a core of crystalline sapphire (Al2O3) material. Then, a thin layer of the material is separated from the bulk substrate by performing a controlled cleaving process along a cleave region formed by particles implanted from the beam. Embodiments may find particular use as hard, scratch-resistant covers for personal electric device displays, or as optical surfaces for fingerprint, eye, or other biometric scanning.Type: GrantFiled: February 13, 2013Date of Patent: May 10, 2016Assignee: SILICON GENESIS CORPORATIONInventor: Francois J. Henley
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Patent number: 9257339Abstract: Embodiments relate to use of a particle accelerator beam to form thin films of material from a bulk substrate are described. In particular embodiments, a bulk substrate having a top surface is exposed to a beam of accelerated particles. In certain embodiments, this bulk substrate may comprise GaN; in other embodiments this bulk substrate may comprise (111) single crystal silicon. Then, a thin film or wafer of material is separated from the bulk substrate by performing a controlled cleaving process along a cleave region formed by particles implanted from the beam. In certain embodiments this separated material is incorporated directly into an optoelectronic device, for example a GaN film cleaved from GaN bulk material. In some embodiments, this separated material may be employed as a template for further growth of semiconductor materials (e.g. GaN) that are useful for optoelectronic devices.Type: GrantFiled: May 2, 2013Date of Patent: February 9, 2016Assignee: SILICON GENESIS CORPORATIONInventors: Francois J. Henley, Sien Kang, Albert Lamm
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Patent number: 9159605Abstract: A method for forming a multi-material thin film includes providing a multi-material donor substrate comprising single crystal silicon and an overlying film comprising GaN. Energetic particles are introduced through a surface of the multi-material donor substrate to a selected depth within the single crystal silicon. The method includes providing energy to a selected region of the donor substrate to initiate a controlled cleaving action in the donor substrate. Then, a cleaving action is made using a propagating cleave front to free a multi-material film from a remaining portion of the donor substrate, the multi-material film comprising single crystal silicon and the overlying film.Type: GrantFiled: August 28, 2014Date of Patent: October 13, 2015Assignee: SILICON GENESIS CORPORATIONInventors: Francois J. Henley, Nathan Cheung
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Publication number: 20120234887Abstract: A thickness of material may be detached from a substrate along a cleave plane, utilizing a cleaving process controlled by a releasable constraint plate. In some embodiments this constraint plate may comprise a plate that can couple side forces (the “P-plate”) and a thin, softer compliant layer (the “S-layer”) situated between the P-plate and the substrate. In certain embodiments a porous surface within the releasable constraint plate and in contact to the substrate, allows the constraint plate to be secured to the substrate via a first pressure differential. Application of a combination of a second pressure differential within a pre-existing cleaved portion, and a linear force to a side of the releasable constraint plate bound to the substrate, generates loading that results in controlled cleaving along the cleave plane.Type: ApplicationFiled: September 2, 2011Publication date: September 20, 2012Applicant: SILICON GENESIS CORPORATIONInventors: Francois Henley, Al Lamm, Yi-Lei Chow
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Publication number: 20020173872Abstract: A computer-readable memory product containing a program suitable for controlling a substrate surface finishing apparatus. In one embodiment, the computer-readable memory product contains program code suitable for re-configuring, with appropriate apparatus component changes, a double-brush scrubber into a touch polish surface finishing system. In another embodiment, the computer-readable memory product contains program code suitable for controlling a substrate surface finishing system to selectively process a portion or portions of the substrate, such as removing a ridge of material from a perimeter portion of the substrate, or smoothing a step between a thin film layer bonded to a handle wafer.Type: ApplicationFiled: July 11, 2002Publication date: November 21, 2002Applicant: SILICON GENESISInventor: Igor J. Malik