Patents Assigned to Silicon Genesis Corporation
  • Patent number: 11901351
    Abstract: Forming a 3DIC includes providing a lower device structure comprising a first substrate with a circuit layer, providing an interconnect network layer having an interconnect structure with a first coupled to a second plurality of electrodes by connection structures on a semiconductor substrate, the first plurality of electrodes being exposed on a first surface of the interconnect layer, implanting ions through the interconnect structure to form a cleave plane in the semiconductor substrate, bonding the interconnect structure to the lower device structure so that electrodes of the first plurality of electrodes are coupled to corresponding electrodes on the lower device structure, cleaving the substrate of the bonded interconnect layer at the cleave plane, removing material from the semiconductor substrate until the second plurality of electrodes is exposed, and bonding an upper device layer to the interconnect structure.
    Type: Grant
    Filed: August 8, 2022
    Date of Patent: February 13, 2024
    Assignee: Silicon Genesis Corporation
    Inventors: Michael I. Current, Theodore E. Fong
  • Patent number: 11626392
    Abstract: A method of forming a semiconductor device includes providing a semiconductor substrate with a circuit layer, forming a range compensating layer over the semiconductor substrate, the range compensating layer having a plurality of different thicknesses, each of the plurality of different thicknesses being inversely proportional to a stopping power of structures disposed under the respective thickness of the range compensating layer, implanting ions into the semiconductor substrate, the ions traveling through the range compensating layer and the circuit layer to define a cleave plane in the semiconductor substrate, removing the range compensating layer, and cleaving the semiconductor substrate at the cleave plane. The range compensating layer can be used to compensate for variations in ion penetration depth.
    Type: Grant
    Filed: February 12, 2021
    Date of Patent: April 11, 2023
    Assignee: Silicon Genesis Corporation
    Inventors: Theodore E. Fong, Michael I. Current
  • Patent number: 11444221
    Abstract: A film of material may be formed by providing a semiconductor substrate having a surface region and a cleave region located at a predetermined depth beneath the surface region. During a process of cleaving the film from the substrate, shear in the cleave region is carefully controlled. According to certain embodiments, an in-plane shear component (KII) is maintained near zero, sandwiched between a tensile region and a compressive region. In one embodiment, cleaving can be accomplished using a plate positioned over the substrate surface. The plate serves to constrain movement of the film during cleaving, and together with a localized thermal treatment reduces shear developed during the cleaving process. According to other embodiments, the KII component is purposefully maintained at a high level and serves to guide and drive fracture propagation through the cleave sequence.
    Type: Grant
    Filed: July 5, 2019
    Date of Patent: September 13, 2022
    Assignee: Silicon Genesis Corporation
    Inventor: Francois J. Henley
  • Patent number: 11410984
    Abstract: Forming a 3DIC includes providing a lower device structure comprising a first substrate with a circuit layer, providing an interconnect network layer having an interconnect structure with a first coupled to a second plurality of electrodes by connection structures on a semiconductor substrate, the first plurality of electrodes being exposed on a first surface of the interconnect layer, implanting ions through the interconnect structure to form a cleave plane in the semiconductor substrate, bonding the interconnect structure to the lower device structure so that electrodes of the first plurality of electrodes are coupled to corresponding electrodes on the lower device structure, cleaving the substrate of the bonded interconnect layer at the cleave plane, removing material from the semiconductor substrate until the second plurality of electrodes is exposed, and bonding an upper device layer to the interconnect structure.
    Type: Grant
    Filed: October 8, 2021
    Date of Patent: August 9, 2022
    Assignee: Silicon Genesis Corporation
    Inventors: Michael I. Current, Theodore E. Fong
  • Patent number: 10923459
    Abstract: Implanting ions to form a cleave layer in a semiconductor device causes damage to sensitive materials such as high-K dielectrics. In a process for forming a cleave layer and repairing damage caused by ion implantation, ions are implanted through a circuit layer of a substrate to form a cleave plane. The substrate is exposed to a hydrogen gas mixture for a first time at a first temperature to repair damage caused by the implanted ions. A cleaving process may then be performed, and the cleaved substrate may be stacked in a 3DIC structure.
    Type: Grant
    Filed: February 21, 2020
    Date of Patent: February 16, 2021
    Assignee: Silicon Genesis Corporation
    Inventors: Theodore E. Fong, Michael I. Current
  • Patent number: 10804252
    Abstract: A method of forming a device includes providing a first substrate having a first area and a second area, forming a range compensating material over the first substrate so that the first material is disposed over the first area and not disposed over the second area, implanting ions into the first area and the second area to form first and second cleave planes at first and second depths, respectively, each of the first and second cleave planes being defined by a concentration of the implanted ions, removing the range compensating material, and cleaving the first substrate along a cleave profile including the first and second cleave planes.
    Type: Grant
    Filed: February 14, 2020
    Date of Patent: October 13, 2020
    Assignee: Silicon Genesis Corporation
    Inventors: Theodore E. Fong, Michael I. Current
  • Patent number: 10683588
    Abstract: A shaped crystalline ingot for an ion cleaving process has a major surface that is substantially planar, a first side face that is substantially planar along a first direction orthogonal to the major surface, and a second side face that is substantially planar along a second direction orthogonal to the major surface. The ion cleaving process is a process in which ions are implanted into the shaped crystalline ingot to form a cleave plane that separates a substrate comprising the major surface from the shaped crystalline ingot.
    Type: Grant
    Filed: September 7, 2018
    Date of Patent: June 16, 2020
    Assignee: Silicon Genesis Corporation
    Inventor: Francois J. Henley
  • Patent number: 10573627
    Abstract: Implanting ions to form a cleave layer in a semiconductor device causes damage to sensitive materials such as high-K dielectrics. In a process for forming a cleave layer and repairing damage caused by ion implantation, ions are implanted through a circuit layer of a substrate to form a cleave plane. The substrate is exposed to a hydrogen gas mixture for a first time at a first temperature to repair damage caused by the implanted ions. A cleaving process may then be performed, and the cleaved substrate may be stacked in a 3DIC structure.
    Type: Grant
    Filed: August 7, 2018
    Date of Patent: February 25, 2020
    Assignee: Silicon Genesis Corporation
    Inventors: Theodore E. Fong, Michael I. Current
  • Patent number: 10087551
    Abstract: A method for slicing a crystalline material ingot includes providing a crystalline material boule characterized by a cropped structure including a first end-face, a second end-face, and a length along an axis in a first crystallographic direction extending from the first end-face to the second end-face. The method also includes cutting the crystalline material boule substantially through a first crystallographic plane in parallel to the axis to separate the crystalline material boule into a first portion with a first surface and a second portion with a second surface. The first surface and the second surface are planar surfaces substantially along the first crystallographic plane. The method further includes exposing either the first surface of the first portion or the second surface of the second portion, and performing a layer transfer process to form a crystalline material sheet from either the first surface of the first portion or from the second surface of the second portion.
    Type: Grant
    Filed: September 13, 2016
    Date of Patent: October 2, 2018
    Assignee: SILICON GENESIS CORPORATION
    Inventor: Francois J. Henley
  • Patent number: 10049915
    Abstract: A stacked semiconductor device is formed by implanting ions through dielectric and conductive structures of a first substrate to define a cleave plane in the first substrate, cleaving the first substrate at the cleave plane to obtain a cleaved layer including the dielectric and conductive structures, bonding at least one die to the first substrate, the at least one die having a smaller width than a width of the first substrate, depositing a planarization material over the at least one die, planarizing the planarization material to form a planarized upper surface over the at least one die, and stacking a third substrate on the planarized upper surface.
    Type: Grant
    Filed: December 1, 2017
    Date of Patent: August 14, 2018
    Assignee: SILICON GENESIS CORPORATION
    Inventors: Theodore E. Fong, Michael I. Current
  • Patent number: 9704835
    Abstract: A method comprises providing a first substrate having dielectric structures and conductive structures. Ions are implanted into the first substrate, the ions traveling through the dielectric structures and the conductive structures to define a cleave plane in the first substrate. The first substrate is cleaved at the cleave plane to obtain a cleaved layer having the dielectric structure and the conductive structures. The cleaved layer is used to form a three-dimensional integrated circuit device having a plurality of stacked integrated circuit (IC) layers, the cleaved layer being one of the stacked IC layers.
    Type: Grant
    Filed: January 11, 2016
    Date of Patent: July 11, 2017
    Assignee: SILICON GENESIS CORPORATION
    Inventors: Theodore E. Fong, Michael I. Current
  • Patent number: 9640711
    Abstract: A thickness of material may be detached from a substrate along a cleave plane, utilizing a cleaving process controlled by a releasable constraint plate. In some embodiments this constraint plate may comprise a plate that can couple side forces (the “P-plate”) and a thin, softer compliant layer (the “S-layer”) situated between the P-plate and the substrate. In certain embodiments a porous surface within the releasable constraint plate and in contact to the substrate, allows the constraint plate to be secured to the substrate via a first pressure differential. Application of a combination of a second pressure differential within a pre-existing cleaved portion, and a linear force to a side of the releasable constraint plate bound to the substrate, generates loading that results in controlled cleaving along the cleave plane.
    Type: Grant
    Filed: May 27, 2016
    Date of Patent: May 2, 2017
    Assignee: Silicon Genesis Corporation
    Inventors: Francois Henley, Al Lamm, Yi-Lei Chow
  • Patent number: 9460908
    Abstract: A method for slicing a crystalline material ingot includes providing a crystalline material boule characterized by a cropped structure including a first end-face, a second end-face, and a length along an axis in a first crystallographic direction extending from the first end-face to the second end-face. The method also includes cutting the crystalline material boule substantially through a first crystallographic plane in parallel to the axis to separate the crystalline material boule into a first portion with a first surface and a second portion with a second surface. The first surface and the second surface are planar surfaces substantially along the first crystallographic plane. The method further includes exposing either the first surface of the first portion or the second surface of the second portion, and performing a layer transfer process to form a crystalline material sheet from either the first surface of the first portion or from the second surface of the second portion.
    Type: Grant
    Filed: December 13, 2013
    Date of Patent: October 4, 2016
    Assignee: Silicon Genesis Corporation
    Inventor: Francois J. Henley
  • Patent number: 9362439
    Abstract: A film of material may be formed by providing a semiconductor substrate having a surface region and a cleave region located at a predetermined depth beneath the surface region. During a process of cleaving the film from the substrate, shear in the cleave region is carefully controlled. According to certain embodiments, an in-plane shear component (KII) is maintained near zero, sandwiched between a tensile region and a compressive region. In one embodiment, cleaving can be accomplished using a plate positioned over the substrate surface. The plate serves to constrain movement of the film during cleaving, and together with a localized thermal treatment reduces shear developed during the cleaving process. According to other embodiments, the KII component is purposefully maintained at a high level and serves to guide and drive fracture propagation through the cleave sequence.
    Type: Grant
    Filed: May 4, 2009
    Date of Patent: June 7, 2016
    Assignee: SILICON GENESIS CORPORATION
    Inventor: Francois J. Henley
  • Patent number: 9356181
    Abstract: A thickness of material may be detached from a substrate along a cleave plane, utilizing a cleaving process controlled by a releasable constraint plate. In some embodiments this constraint plate may comprise a plate that can couple side forces (the “P-plate”) and a thin, softer compliant layer (the “S-layer”) situated between the P-plate and the substrate. In certain embodiments a porous surface within the releasable constraint plate and in contact to the substrate, allows the constraint plate to be secured to the substrate via a first pressure differential. Application of a combination of a second pressure differential within a pre-existing cleaved portion, and a linear force to a side of the releasable constraint plate bound to the substrate, generates loading that results in controlled cleaving along the cleave plane.
    Type: Grant
    Filed: February 10, 2015
    Date of Patent: May 31, 2016
    Assignee: SILICON GENESIS CORPORATION
    Inventors: Francois Henley, Al Lamm, Yi-Lei Chow
  • Patent number: 9336989
    Abstract: Embodiments relate to use of a particle accelerator beam to form thin layers of material from a bulk substrate. In particular embodiments, a bulk substrate (e.g. donor substrate) having a top surface is exposed to a beam of accelerated particles. In certain embodiments, this bulk substrate may comprise a core of crystalline sapphire (Al2O3) material. Then, a thin layer of the material is separated from the bulk substrate by performing a controlled cleaving process along a cleave region formed by particles implanted from the beam. Embodiments may find particular use as hard, scratch-resistant covers for personal electric device displays, or as optical surfaces for fingerprint, eye, or other biometric scanning.
    Type: Grant
    Filed: February 13, 2013
    Date of Patent: May 10, 2016
    Assignee: SILICON GENESIS CORPORATION
    Inventor: Francois J. Henley
  • Patent number: 9257339
    Abstract: Embodiments relate to use of a particle accelerator beam to form thin films of material from a bulk substrate are described. In particular embodiments, a bulk substrate having a top surface is exposed to a beam of accelerated particles. In certain embodiments, this bulk substrate may comprise GaN; in other embodiments this bulk substrate may comprise (111) single crystal silicon. Then, a thin film or wafer of material is separated from the bulk substrate by performing a controlled cleaving process along a cleave region formed by particles implanted from the beam. In certain embodiments this separated material is incorporated directly into an optoelectronic device, for example a GaN film cleaved from GaN bulk material. In some embodiments, this separated material may be employed as a template for further growth of semiconductor materials (e.g. GaN) that are useful for optoelectronic devices.
    Type: Grant
    Filed: May 2, 2013
    Date of Patent: February 9, 2016
    Assignee: SILICON GENESIS CORPORATION
    Inventors: Francois J. Henley, Sien Kang, Albert Lamm
  • Patent number: 9159605
    Abstract: A method for forming a multi-material thin film includes providing a multi-material donor substrate comprising single crystal silicon and an overlying film comprising GaN. Energetic particles are introduced through a surface of the multi-material donor substrate to a selected depth within the single crystal silicon. The method includes providing energy to a selected region of the donor substrate to initiate a controlled cleaving action in the donor substrate. Then, a cleaving action is made using a propagating cleave front to free a multi-material film from a remaining portion of the donor substrate, the multi-material film comprising single crystal silicon and the overlying film.
    Type: Grant
    Filed: August 28, 2014
    Date of Patent: October 13, 2015
    Assignee: SILICON GENESIS CORPORATION
    Inventors: Francois J. Henley, Nathan Cheung
  • Patent number: 8993410
    Abstract: A thickness of material may be detached from a substrate along a cleave plane, utilizing a cleaving process controlled by a releasable constraint plate. In some embodiments this constraint plate may comprise a plate that can couple side forces (the “P-plate”) and a thin, softer compliant layer (the “S-layer”) situated between the P-plate and the substrate. In certain embodiments a porous surface within the releasable constraint plate and in contact to the substrate, allows the constraint plate to be secured to the substrate via a first pressure differential. Application of a combination of a second pressure differential within a pre-existing cleaved portion, and a linear force to a side of the releasable constraint plate bound to the substrate, generates loading that results in controlled cleaving along the cleave plane.
    Type: Grant
    Filed: September 2, 2011
    Date of Patent: March 31, 2015
    Assignee: Silicon Genesis Corporation
    Inventors: Francois Henley, Al Lamm, Yi-Lei Chow
  • Patent number: 8835282
    Abstract: A method for forming a multi-material thin film includes providing a multi-material donor substrate comprising single crystal silicon and an overlying film comprising GaN. Energetic particles are introduced through a surface of the multi-material donor substrate to a selected depth within the single crystal silicon. The method includes providing energy to a selected region of the donor substrate to initiate a controlled cleaving action in the donor substrate. Then, a cleaving action is made using a propagating cleave front to free a multi-material film from a remaining portion of the donor substrate, the multi-material film comprising single crystal silicon and the overlying film.
    Type: Grant
    Filed: January 16, 2013
    Date of Patent: September 16, 2014
    Assignee: Silicon Genesis Corporation
    Inventors: Francois J. Henley, Nathan Cheung