Patents Assigned to Silicon Graphic, Inc.
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Patent number: 8078907Abstract: A cpu-set type multiprocessor system allows a cpu of a cpu-set that has a hardware exception to disable itself and notify the system. The system assigns processes of the cpu-set that include the problem cpu to another cpu-set. The disabling of the problem cpu and transfer of the related processes to another cpu-set allows the system to failsoft so that other cpu-sets the multiprocessor system can continue to run and a recovery of the processes being run on the problem cpu-set occurs.Type: GrantFiled: January 19, 2006Date of Patent: December 13, 2011Assignee: Silicon Graphics, Inc.Inventors: Patrick John Donlin, Samuel Edward Watters
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Patent number: 8031823Abstract: A system and method of reducing skew between a plurality of signals transmitted with a transmit clock is described. Skew is detected between the received transmit clock and each of received data signals. Delay is added to the clock or to one or more of the plurality of data signals to compensate for the detected skew. The delay added to each of the plurality of delayed signals is updated to adapt to changes in detected skew.Type: GrantFiled: October 7, 2008Date of Patent: October 4, 2011Assignee: Silicon Graphics, Inc.Inventors: Philip Nord Jenkins, Frank N. Cornett
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Publication number: 20110214007Abstract: A system for implementing a failover policy includes a cluster infrastructure for managing a plurality of nodes, a high availability infrastructure for providing group and cluster membership services, and a high availability script execution component operative to receive a failover script and at least one failover attribute and operative to produce a failover domain. In addition, a method for determining a target node for a failover comprises executing a failover script that produces a failover domain, the failover domain having an ordered list of nodes, receiving a failover attribute and based on the failover attribute and failover domain, selecting a node upon which to locate a resource.Type: ApplicationFiled: September 27, 2010Publication date: September 1, 2011Applicant: Silicon Graphics, Inc.Inventors: Padmanabhan Sreenivasan, Ajit Dandapani, Michael Nishimoto, Ira Pramanick, Manish Verma, Robert David Bradshaw, Luca Castellano, Raghu Mallena
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Publication number: 20100154054Abstract: A cluster of computer system nodes share direct read/write access to storage devices via a storage area network using a cluster filesystem. At least one trusted metadata server assigns a mandatory access control label as an extended attribute of each filesystem object regardless of whether required by a client node accessing the filesystem object. The mandatory access control label indicates the sensitivity and integrity of the filesystem object and is used by the trusted metadata server(s) to control access to the filesystem object by all client nodes.Type: ApplicationFiled: December 29, 2009Publication date: June 17, 2010Applicant: Silicon Graphics, Inc.Inventor: Kenneth S. Beck
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Publication number: 20100146045Abstract: A cluster of computer system nodes connected by a storage area network include two classes of nodes. The first class of nodes can act as clients or servers, while the other nodes can only be clients. The client-only nodes require much less functionality and can be more easily supported by different operating systems. To minimize the amount of data transmitted during normal operation, the server responsible for maintaining a cluster configuration database repeatedly multicasts the IP address, its incarnation number and the most recent database generation number. Each node stores this information and when a change is detected, each node can request an update of the data needed by that node. A client-only node uses the IP address of the server to connect to the server, to download the information from the cluster database required by the client-only node and to upload local disk connectivity information.Type: ApplicationFiled: November 10, 2009Publication date: June 10, 2010Applicant: Silicon Graphics, Inc.Inventors: Daniel Moore, Andrew Gildfind
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Publication number: 20100110062Abstract: An image display system synchronizes the display of images on a plurality of display devices. The method entails generating at a first computer system a first signal representing first image data to be displayed on a first display device, generating at a second computer system a second signal representing second image data to be displayed on a second display device, and a method for synchronizing the first and second image data. The synchronizing method includes using a phase-locked loop circuit having a digital rate controller. The digital rate controller allows programmable control of the speed of the phase-locked loop.Type: ApplicationFiled: February 26, 2009Publication date: May 6, 2010Applicant: Silicon Graphics, Inc.Inventors: Joseph P. Kennedy, John A. Klenoski, Greg Sadowski
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Patent number: 7627694Abstract: A high availability computing system includes a plurality of computer nodes (for example, a server system) connected by a first and a second network, wherein the computer nodes communicate with each other to detect server failure and transfer applications to other computer nodes on detecting server failure. The system incorporates methods of maintaining high availability in a server cluster having a plurality of nodes. A group communications service, a membership service and a system resource manager are instantiated on each node and the group communications service, the membership service and the system resource manager on each node communicate with other nodes to detect node failures and to transfer applications to other nodes on detecting node failure.Type: GrantFiled: March 16, 2001Date of Patent: December 1, 2009Assignee: Silicon Graphics, Inc.Inventors: Padmanabhan Sreenivasan, Ajit Dandapani, Michael Nishimoto, Ira Pramanick, Manish Verma, Robert David Bradshaw, Luca Castellano, Sharad Srivastava, Raghu Mallena
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Publication number: 20090276555Abstract: An apparatus for controlling a hot plug bus slot on a bus has an input for receiving a set of float signals (i.e., the set may have one or more float signals), and a driver having an output electrically couplable with the bus. The apparatus also has float logic operatively coupled with the input. The float logic is responsive to the set of float signals to cause the output to float at a high impedance in response to receipt of the set of float signals.Type: ApplicationFiled: May 11, 2009Publication date: November 5, 2009Applicant: Silicon Graphics, Inc.Inventors: Bruce A. Strangfeld, Thomas E. McGee
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Publication number: 20090259696Abstract: A method and apparatus for controlling access by a set of accessing nodes to memory of a home node (in a multimode computer system) determines that each node in the set of nodes has accessed the memory, and forwards a completion message to each node in the set of nodes after it is determined that each node has accessed the memory. The completion message has data indicating that each node in the set of nodes has accessed the memory of the home node.Type: ApplicationFiled: December 8, 2008Publication date: October 15, 2009Applicant: SILICON GRAPHICS, INC.Inventors: John Carter, Randal S. Passint, Donglai Dai, Zhen Fang, Lixin Zhang, Gregory M. Thorson
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Patent number: 7603573Abstract: A system and method of designing a computer system having a plurality of processors. A computational density is selected for the computer system, wherein the computational density is expressed as a function of a desired computational power for a given volume. A number of processors is selected for used in the computer system and the desired computational power is allocated across the selected number of processors. One or more constraints are selected and a particular processor is designed or selected to meet the allocated processor computational power and the constraint.Type: GrantFiled: October 24, 2006Date of Patent: October 13, 2009Assignee: Silicon Graphics, Inc.Inventor: Eng Lim Goh
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Patent number: 7593968Abstract: A cluster of computer system nodes share direct read/write access to storage devices via a storage area network using a cluster filesystem. During relocation of a server for a distributed name service and recovery of a cluster, entries related to the distributed name service for filesystems is updated. During relocation, a new server for a filesystem informs all nodes in the cluster of the new server's location. During recovery, a process executing on each node deletes entries related to the distributed name service for any filesystem that does not have a server in the recovering cluster.Type: GrantFiled: January 16, 2003Date of Patent: September 22, 2009Assignee: Silicon Graphics, Inc.Inventor: Ken Beck
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Publication number: 20090222821Abstract: Processing transaction requests in a shared memory multi-processor computer network is described. A transaction request is received at a servicing agent from a requesting agent. The transaction request includes a request priority associated with a transaction urgency generated by the requesting agent. The servicing agent provides an assigned priority to the transaction request based on the request priority, and then compares the assigned priority to an existing service level at the servicing agent to determine whether to complete or reject the transaction request. A reply message from the servicing agent to the requesting agent is generated to indicate whether the transaction request was completed or rejected, and to provide reply fairness state data for rejected transaction requests.Type: ApplicationFiled: February 28, 2008Publication date: September 3, 2009Applicant: SILICON GRAPHICS, INC.Inventors: Eric C. Fromm, Gregory M. Thorson
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Patent number: 7533208Abstract: An apparatus for controlling a hot plug bus slot on a bus has an input for receiving a set of float signals (i.e., the set may have one or more float signals), and a driver having an output electrically couplable with the bus. The apparatus also has float logic operatively coupled with the input. The float logic is responsive to the set of float signals to cause the output to float at a high impedance in response to receipt of the set of float signals.Type: GrantFiled: September 26, 2005Date of Patent: May 12, 2009Assignee: Silicon Graphics, Inc.Inventors: Bruce A. Strangfeld, Thomas E. McGee
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Patent number: 7526125Abstract: The present invention provides for a method of and apparatus for compressing and uncompressing image data. According to one embodiment of the present invention, the method of compressing a color cell comprises the steps of: defining at least four luminance levels of the color cell; generating a bitmask for the color cell, the bitmask having a plurality of entries each corresponding to a respective one of the pixels, each of the entries for storing data identifying one of the luminance levels associated with a corresponding one of the pixels; calculating a first average color of pixels associated with a first one of the luminance levels; calculating a second average color of pixels associated with a second one of the luminance levels; and storing the bitmask in association with the first average color and the second average color.Type: GrantFiled: February 11, 2008Date of Patent: April 28, 2009Assignee: Silicon Graphics, Inc.Inventors: Robert A. Drebin, David Wang, Christopher J. Migdal
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Patent number: 7518615Abstract: A floating point rasterization and frame buffer in a computer system graphics program. The rasterization, fog, lighting, texturing, blending, and antialiasing processes operate on floating point values. In one embodiment, a 16-bit floating point format consisting of one sign bit, ten mantissa bits, and five exponent bits (s10e5), is used to optimize the range and precision afforded by the 16 available bits of information. In other embodiments, the floating point format can be defined in the manner preferred in order to achieve a desired range and precision of the data stored in the frame buffer. The final floating point values corresponding to pixel attributes are stored in a frame buffer and eventually read and drawn for display. The graphics program can operate directly on the data in the frame buffer without losing any of the desired range and precision of the data.Type: GrantFiled: July 12, 2000Date of Patent: April 14, 2009Assignee: Silicon Graphics, Inc.Inventors: John M. Airey, Mark S. Peercy, Robert A. Drebin, John Montrym, David L. Dignam, Christopher J. Migdal, Danny D. Loh
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Patent number: 7499044Abstract: An image display system synchronizes the display of images on a plurality of display devices. The system includes a first computer system generating a first signal representing first image data to be displayed on a first display device, a second computer system generating a second signal representing second image data to be displayed on a second display device, and means for synchronizing the first and second image data. The synchronizing means includes a phase-locked loop circuit having a digital rate controller. The digital rate controller allows programmable control of the speed of the phase-locked loop.Type: GrantFiled: October 30, 2003Date of Patent: March 3, 2009Assignee: Silicon Graphics, Inc.Inventors: Joseph P Kennedy, John A Klenoski, Greg Sadowski
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Patent number: 7500068Abstract: A method and system for managing memory in a multiprocessor system includes defining the plurality of processor coherence domains within a system coherence domain of the multiprocessor system. The processor coherence domains each include a plurality of processors and a processor memory. Shared access to data in the processor memory of each processor coherence domain is provided only to elements of the multiprocessor system within the processor coherence domain. Non-shared access to data in the processor memory of each processor coherence domain is provided to elements of the multiprocessor system within and outside of the processor coherence domain.Type: GrantFiled: June 26, 2006Date of Patent: March 3, 2009Assignee: Silicon Graphics, Inc.Inventors: Daniel E. Lenoski, Jeffrey S. Kuskin, William A. Huffman, Michael S. Woodacre
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Publication number: 20090051711Abstract: A compact flat panel color calibration system includes a lens prism optic able to pass a narrow, perpendicular, and uniform cone angle of incoming light to a spectrally non-selective photodetector. The calibration system also includes a microprocessor operable to determine the luminance of the display based upon the information gathered by the photodetector. A software module included in the calibration system is then operable to process the luminance information in order to adjust the flat panel display.Type: ApplicationFiled: July 29, 2008Publication date: February 26, 2009Applicant: Silicon Graphics, Inc.Inventors: Daniel Evanicky, Ed Granger, Joel Ingulsrud, Alice T. Meng
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Publication number: 20090034673Abstract: A system and method of reducing skew between a plurality of signals transmitted with a transmit clock is described. Skew is detected between the received transmit clock and each of received data signals. Delay is added to the clock or to one or more of the plurality of data signals to compensate for the detected skew. The delay added to each of the plurality of delayed signals is updated to adapt to changes in detected skew.Type: ApplicationFiled: October 7, 2008Publication date: February 5, 2009Applicant: Silicon Graphics, Inc.Inventors: Philip Nord Jenkins, Frank N. Cornett
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Patent number: 7485003Abstract: A cable connector assembly for high frequency applications having reduced electromagnetic emissions. Aspects include providing physical spacing and electrical isolation between the signal conductors and a conductive housing. An isolative member provides reduced capacitive coupling. One embodiment includes spring preloading of the electrical connector relative to the housing. One embodiment includes a connector floating longitudinally within a conductive housing.Type: GrantFiled: September 5, 2002Date of Patent: February 3, 2009Assignee: Silicon Graphics, Inc.Inventors: Val Mandrusov, Duane Friesen