Abstract: An electrical connector (10) includes a cable dock (12) having a first connector (16) and a backshell assembly (14) having a second connector (18). The second connector (18) is adapted for engagement with the first connector (16). The electrical connector (10) also includes a locking element (40) coupled to the cable dock (12) and a latch (46) coupled to the backshell assembly (14). The latch (46) is operable to engage the locking element (40) and, in response to movement of the latch (46) relative to the backshell assembly (14), engage the first connector (16) with the second connector (18).
Type:
Grant
Filed:
June 30, 2000
Date of Patent:
September 25, 2001
Assignee:
Silicon Graphics
Inventors:
Andrew L. Johnston, David C. North, Bruce R. Garrett
Abstract: Techniques for providing a number of precisely synchronized clock signals at a number of different frequencies at each of a plurality of locations on a chip. A number of synchronized clock signals are generated at an initial location on the chip, and distributed to the various locations with relative delay times that are equal to within a precision, which may be less than the ultimate precision required. A single synchronization signal is also generated at the initial location, and is distributed to the remote locations with delay times that are equal to each other to a precision that corresponds to the precision required of all the clock signals. Separate synchronization circuitry at each remote location receives the clock signals and the synchronization signal, and resynchronizes the clock signals to the precision with which the synchronization signal was distributed. The set of lines is configured as a tree structure.
Type:
Grant
Filed:
August 21, 1992
Date of Patent:
May 31, 1994
Assignee:
Silicon Graphics
Inventors:
Thomas J. Riordan, Albert M. Thaik, Hai N. Nguyen