Patents Assigned to Silicon Graphics International
  • Patent number: 9665923
    Abstract: A system, method, and computer program product are provided for remote rendering of computer graphics. The system includes a graphics application program resident at a remote server. The graphics application is invoked by a user or process located at a client. The invoked graphics application proceeds to issue graphics instructions. The graphics instructions are received by a remote rendering control system. Given that the client and server differ with respect to graphics context and image processing capability, the remote rendering control system modifies the graphics instructions in order to accommodate these differences. The modified graphics instructions are sent to graphics rendering resources, which produce one or more rendered images. Data representing the rendered images is written to one or more frame buffers. The remote rendering control system then reads this image data from the frame buffers. The image data is transmitted to the client for display or processing.
    Type: Grant
    Filed: January 4, 2016
    Date of Patent: May 30, 2017
    Assignee: Silicon Graphics International Corp.
    Inventor: Phillip C. Keslin
  • Patent number: 9632934
    Abstract: A high performance computing system and methods are disclosed. The system includes logical partitions with physically removable nodes that each have at least one processor, and memory that can be shared with other nodes. Node hardware may be removed or allocated to another partition without a reboot or power cycle. Memory sharing is tracked using a memory directory. Cache coherence operations on the memory directory include a test to determine whether a given remote node has been removed. If the remote node is not present, system hardware simulates a valid response from the missing node.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: April 25, 2017
    Assignee: Silicon Graphics International Corp.
    Inventor: Brian J. Johnson
  • Patent number: 9619180
    Abstract: The present system enables more efficient I/O processing by providing a mechanism for maintaining data within the locality of reference. One or more accelerator modules may be implemented within a solid state storage device (SSD). The accelerator modules form a caching storage tier that can receive, store and reproduce data. The one or more accelerator modules may place data into the SSD or hard disk drives based on parameters associated with the data.
    Type: Grant
    Filed: July 18, 2014
    Date of Patent: April 11, 2017
    Assignee: Silicon Graphics International Corp.
    Inventor: Kirill Malkin
  • Patent number: 9619288
    Abstract: A system for deploying big data software in a multi-instance node. The optimal CPU memory and core configuration for a single instance database is determined. After determining an optimal core-memory ratio for a single instance execution, the software is deployed in multi-instance mode on single machine by applying the optimal core-memory ratio for each of the instances. The multi-instance database may then be deployed and data may be loaded in parallel for the instances.
    Type: Grant
    Filed: July 28, 2016
    Date of Patent: April 11, 2017
    Assignee: Silicon Graphics International Corp.
    Inventors: Sanhita Sarkar, Raymon Morcos
  • Patent number: 9612745
    Abstract: Embodiments of the presently claimed invention enable a RAID set to appear as if it were initialized immediately after a command to initialize a RAID set is initiated. Typically, a driver or other software in the software stack intercepts the command to initialize the RAID set. The driver then responds to user application programs as if the RAID set initialization is complete, even when it is not. After intercepting the RAID set initialization command, the driver will intercept and respond to data read or write commands as if the RAID set were initialized. The driver or other software will then, typically initialize the RAID set using background tasks. In certain instances, data stored in a non-RAID configuration may be migrated to a RAID configuration during the initialization process.
    Type: Grant
    Filed: January 24, 2014
    Date of Patent: April 4, 2017
    Assignee: Silicon Graphics International Corp.
    Inventor: Larry Fenske
  • Patent number: 9613035
    Abstract: A primary data storage system is connected with a separate and external active archive storage system to consolidate data and allow active archive data to be managed based on primary storage system events. The primary data storage system may be managed and maintained by an external entity, and may include a manager module such as a resource manager. The active archive system may include several tiers of storage in a hierarchical storage system and logic for moving data between and among the tiers. As data processing milestones are completed or the state of data changes, in projects stored in the primary data storage system, task milestone or state change events are detected. Event detection can trigger data movement in the active archive solution. One or more software modules implementing the present invention may detect the events and trigger active archive operations based on the events.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: April 4, 2017
    Assignee: Silicon Graphics International Corp.
    Inventor: Floyd William Christofferson
  • Patent number: 9612920
    Abstract: Data state rollover is performed based on data state snapshots and deltas. A series of snapshots is taken of the current data state, an original data state, and data states in between. Deltas are then generated between two sequential snapshots. This results in numerous deltas which represent the difference between consecutive snapshots. Once the deltas are acquired, the deltas may be stored along with the snapshot of the present data state. As such, previous data states may be rolled back to by determining the number of deltas to apply to the current data state to achieve the desired previous data state. In cases where the rollback or rollover fails, deltas may be played against the current data state to a point where the last known trusted and working data point existed.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: April 4, 2017
    Assignee: Silicon Graphics International Corp.
    Inventors: John Michael Sygulla, Arun Ramakrishnan, Greg Slowiak
  • Patent number: 9606588
    Abstract: A cooling system for a high performance computing system includes a closed-loop cooling cell having two compute racks and a cooling tower between the compute racks. Each compute rack includes at least one blade enclosure, and the cooling tower includes at least one water-cooled heat exchanger and one or more blowers configured to draw warm air from a side of the compute racks towards a back, across the water-cooled heat exchanger, and to circulate cooled air to a side of the compute racks towards a front. The cooling cell further includes a housing enclosing the compute racks and the cooling tower to provide a closed-loop air flow within the cooling cell. The cooling system further includes cooling plate(s) configured to be disposed between two computing boards within the computing blade, and a fluid connection coupled to the cooling plate and in fluid communication with the blade enclosure.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: March 28, 2017
    Assignee: Silicon Graphics International Corp.
    Inventors: Steven J. Dean, David R. Collins, Timothy Scott McCann, Perry D. Franz, Jeffrey M. Glanzman
  • Patent number: 9514092
    Abstract: A system and method for interconnecting a plurality of processing element nodes within a scalable multiprocessor system is provided. Each processing element node includes at least one processor and memory. A scalable interconnect network includes physical communication links interconnecting the processing element nodes in a cluster. A first set of routers in the scalable interconnect network route messages between the plurality of processing element nodes. One or more metarouters in the scalable interconnect network route messages between the first set of routers so that each one of the routers in a first cluster is connected to all other clusters through one or more metarouters.
    Type: Grant
    Filed: April 29, 2013
    Date of Patent: December 6, 2016
    Assignee: Silicon Graphics International Corp.
    Inventors: Martin M. Deneroff, Gregory M. Thorson, Randal S. Passint
  • Patent number: 9477592
    Abstract: A high performance computing (HPC) system includes computing blades having a first region that includes computing circuit boards having processors for performing a computation, and a second region that includes non-volatile memory for use in performing the computation. The regions are connected by a plurality of power connectors that convey power from the computing circuit boards to the memory, and a plurality of data connectors that convey data between the first and second regions. The power and data connectors are configured redundantly so that failure of a computing circuit board, a power connector, or a data connector does not interrupt the computation. A method of performing such a computation, and a computer program product implementing the method, are also disclosed.
    Type: Grant
    Filed: June 29, 2013
    Date of Patent: October 25, 2016
    Assignee: Silicon Graphics International Corp.
    Inventor: Steven Dean
  • Patent number: 9465712
    Abstract: A method and computer program product for testing a high performance computing application performing a computation within a clustered computer arrangement is disclosed. The high performance computing arrangement performances computations across processors in parallel wherein the processors cooperate to perform the computation. The application can be tested by adding delay and therefore latency to one or more commands inside of the precompiled application. The addition of delay can be used to simulate the performance of different interconnects that are used within the high performance computing arrangement.
    Type: Grant
    Filed: June 26, 2013
    Date of Patent: October 11, 2016
    Assignee: Silicon Graphics International Corp.
    Inventors: Daniel Thomas, John Baron
  • Patent number: 9432299
    Abstract: A multiple channel data transfer system (10) includes a source (12) that generates data packets with sequence numbers for transfer over multiple request channels (14). Data packets are transferred over the multiple request channels (14) through a network (16) to a destination (18). The destination (18) re-orders the data packets received over the multiple request channels (14) into a proper sequence in response to the sequence numbers to facilitate data processing. The destination (18) provides appropriate reply packets to the source (12) over multiple response channels (20) to control the flow of data packets from the source (12).
    Type: Grant
    Filed: March 2, 2015
    Date of Patent: August 30, 2016
    Assignee: Silicon Graphics International Corp.
    Inventors: Randal G. Martin, Steven C. Miller, Mark D. Stadler, David A. Kruckemyer
  • Patent number: 9424098
    Abstract: Embodiments of the invention relate to a system and method for dynamically scheduling resources using policies to self-optimize resource workloads in a data center. The object of the invention is to allocate resources in the data center dynamically corresponding to a set of policies that are configured by an administrator. Operational parametrics that correlate to the cost of ownership of the data center are monitored and compared to the set of policies configured by the administrator. When the operational parametrics approach or exceed levels that correspond to the set of policies, workloads in the data center are adjusted with the goal of minimizing the cost of ownership of the data center. Such parametrics include yet are not limited to those that relate to resiliency, power balancing, power consumption, power management, error rate, maintenance, and performance.
    Type: Grant
    Filed: June 29, 2013
    Date of Patent: August 23, 2016
    Assignee: Silicon Graphics International Corp.
    Inventors: Eng Lim Goh, Christian Tanasescu, George L. Thomas, Charlton Port
  • Patent number: 9426932
    Abstract: A server includes a tray that has a front portion and a back portion. A motherboard is disposed in the front portion of the tray and the motherboard is coupled to a heat sink. A fan is disposed in the back portion of the tray. A hard drive is disposed between the motherboard and the fan and the hard drive is operatively connected to the motherboard. The server also includes a heat pipe that has a body longitudinally bounded by an inlet and an outlet. The inlet is coupled to the heat sink, while the outlet is coupled to the fan. The body of the heat pipe extends past the hard drive. A power supply is also disposed in the tray and is operatively connected to the motherboard, the fan, and the hard drive.
    Type: Grant
    Filed: June 29, 2013
    Date of Patent: August 23, 2016
    Assignee: Silicon Graphics International Corp.
    Inventors: Robert Michael Kinstle, Kevin Schlichter, Seitu Barron
  • Patent number: 9405606
    Abstract: A cluster of computer system nodes share direct read/write access to storage devices via a storage area network using a cluster filesystem. At least one trusted metadata server assigns a mandatory access control label as an extended attribute of each filesystem object regardless of whether required by a client node accessing the filesystem object. The mandatory access control label indicates the sensitivity and integrity of the filesystem object and is used by the trusted metadata server(s) to control access to the filesystem object by all client nodes.
    Type: Grant
    Filed: September 30, 2013
    Date of Patent: August 2, 2016
    Assignee: Silicon Graphics International Corp.
    Inventor: Kenneth S. Beck
  • Patent number: 9389760
    Abstract: A system may provide a visualization function during computational functions performed by a host system. Access to a library of functions including a visualization function is provided. Then, a computing application is executed. The execution of the computing application includes generating multi-dimensional data, invoking the visualization function from the library, and providing a visual representation of at least a portion of the multi-dimensional data for display within the computing application using the visualization function.
    Type: Grant
    Filed: June 29, 2013
    Date of Patent: July 12, 2016
    Assignee: Silicon Graphics International Corporation
    Inventors: Eng Lim Goh, Hansong Zhang, Chandrasekhar Murthy
  • Patent number: 9389940
    Abstract: Error data is read from error registers and written into a buffer. A computing node uses a BIOS to read the error data, rearm the error register and write the data into a memory mapped buffer. A hub chip supports creation of a shared memory system of computing nodes. A management controller in the computing node extracts error data from the buffer. The error data preferably consists essentially of the error register identifiers and the contents of the error registers. A system management node receives the error data from the management controllers in the computing nodes. The system management node may be coupled to but separate from the computing nodes.
    Type: Grant
    Filed: February 28, 2013
    Date of Patent: July 12, 2016
    Assignee: Silicon Graphics International Corp.
    Inventors: Mark Larson, Michael Brown, Gary Meyer
  • Patent number: 9367473
    Abstract: A processor (600) in a distributed shared memory multi-processor computer system (10) may initiate a flush request to remove data from its cache. A processor interface (24) receives the flush request and performs a snoop operation to determine whether the data is maintained in a one of the local processors (601) and whether the data has been modified. If the data is maintained locally and it has been modified, the processor interface (24) initiates removal of the data from the cache of the identified processor (601). The identified processor (601) initiates a writeback to a memory directory interface unit (24) associated with a home memory 17 for the data in order to preserve the modification to the data. If the data is not maintained locally or has not been modified, the processor interface (24) forwards the flush request to the memory directory interface unit (22).
    Type: Grant
    Filed: December 26, 2013
    Date of Patent: June 14, 2016
    Assignee: Silicon Graphics International Corp.
    Inventor: Jeffrey S. Kuskin
  • Patent number: 9275058
    Abstract: A cluster of computer system nodes share direct read/write access to storage devices via a storage area network using a cluster filesystem and operating system implementing DMAPI. Threads executing on a metadata client know when a DMAPI event is required, and generate the DMAPI event on their own initiative when necessary. A metadata server maintains DMAPI queues. If the metadata server relocates to another host, the DMAPI events in the DMAPI queues are moved transparently to users.
    Type: Grant
    Filed: August 29, 2011
    Date of Patent: March 1, 2016
    Assignee: Silicon Graphics International Corp.
    Inventors: Geoffrey Wehrman, Dean Roehrich
  • Patent number: 9268684
    Abstract: A high performance computing (HPC) system includes computing blades having a first region that includes processors for performing a computation, and a second region that includes non-volatile memory for use in performing the computation and another computing processor for performing data movement and storage. Because data movement and storage are offloaded to the secondary processor, the processors for performing the computation are not interrupted to perform these tasks. A method for use in the HPC system receives instructions in the computing processors and first data in the memory. The method includes receiving second data into the memory while continuing to execute the instructions in the computing processors, without interruption. A computer program product implementing the method is also disclosed.
    Type: Grant
    Filed: June 29, 2013
    Date of Patent: February 23, 2016
    Assignee: Silicon Graphics International Corp.
    Inventors: Steven Dean, David R. Collins, Paul Kinyon