Abstract: A data processing circuit is described that includes an instruction decoder operable in a first and a second instruction mode. In the first instruction mode instructions have respective fields for controlling each of multiple functional units, and in the second instruction mode instructions controlling only one functional unit. A mode control circuit controls selecting the instruction modes. The instruction decoder uses time-stationary decoding of operations and destination registers. When instructions are scheduled, constraints are imposed on operations for which operation selection and destination register selection are included on different sides of an instruction mode change. When an instruction containing a jump is encountered, the mode control circuit sets the instruction mode for subsequent instructions in conformity with information provided by executing the jump command.

Abstract: An image processing device comprising a synchronization unit (25) for generating a luminance (Y?) from the sum of pixel signals R, Gr, Gb, B, for subtracting the R pixel signal and the B pixel signal from the sum of the Gr pixel signal and Gb pixel signal so as to generate a first color difference (C1), and for calculating a difference between the R pixel signal and the B pixel signal to generate a second color difference (C2), a pseudo-color suppression unit (31) for performing pseudo-color suppression of the first color difference (C1) and/or the second color difference (C2), a color space conversion unit (37) for converting the luminance Y?, the first color difference (C1), the second color difference (C2), into a predetermined color space to generate YUV color information.

Abstract: An image processing device includes: a coordinate conversion unit (142) which calculates a corresponding sampling coordinate on a color mosaic image corresponding to a pixel position of a color image when a deformation process is performed, according to the pixel position of the color image; a sampling unit (143); a sampling unit (143) which interpolates-generates a pixel value in a sampling coordinate for each of color planes obtained by decomposing the color mosaic image; and a color generation unit (144) which generates a color image by synthesizing interpolation values of the respective color planes. Each pixel value of a color image subjected to a deformation process is obtained as a pixel value of the sampling coordinate from the color mosaic image by interpolation calculation, thereby realizing the color interpolation process for generating a color image from the color mosaic image and a deformation process of the color image by one interpolation calculation.

Abstract: A data processing circuit is described that includes an instruction decoder operable in a first and a second instruction mode. In the first instruction mode instructions have respective fields for controlling each of multiple functional units, and in the second instruction mode instructions controlling only one functional unit. A mode control circuit controls selecting the instruction modes. The instruction decoder uses time-stationary decoding of operations and destination registers. When instructions are scheduled, constraints are imposed on operations for which operation selection and destination register selection are included on different sides of an instruction mode change. When an instruction containing a jump is encountered, the mode control circuit sets the instruction mode for subsequent instructions in conformity with information provided by executing the jump command.

Abstract: An image processing device comprising a synchronization unit (25) for generating a luminance (Y?) from the sum of pixel signals R, Gr, Gb, B, for subtracting the R pixel signal and the B pixel signal from the sum of the Gr pixel signal and Gb pixel signal so as to generate a first color difference (C1), and for calculating a difference between the R pixel signal and the B pixel signal to generate a second color difference (C2), a pseudo-color suppression unit (31) for performing pseudo-color suppression of the first color difference (C1) and/or the second color difference (C2), a color space conversion unit (37) for converting the luminance Y?, the first color difference (C1), the second color difference (C2), into a predetermined color space to generate YUV color information.

Abstract: A programmable signal processing circuit is used to (de-)interleave a data stream. Data from the signal stream is stored in a data memory (28) and read in a different sequence. The programmable signal processing circuit is used for computing addresses, for use in said storing and/or reading. The programmable signal processing circuit has an instruction set that contains an instruction to compute the addresses from preceding addresses that have been used for said storing and/or reading. In response to the instruction the programmable signal processing circuit permutes positions of a plurality of bits from the old address operand and forms of a bit of the new address result as a logic function of a combination of bits from the old address operand. Successive addresses are formed by means of repeated execution of a program loop that contains an address update instruction for computing the addresses.

Abstract: Data processing circuit containing an instruction execution circuit having an instruction set comprising a SIMD instruction. The instruction execution circuit comprises arithmetic circuits, arranged to perform N respective identical operations in parallel in response to the SIMD instruction. The SIMD instruction selects a first one and a second one of the registers. The SIMD instruction defines a first and second series of N respective SIMD instruction operands of the SIMD instruction from the addressed registers. Each arithmetic circuit receives a respective first operand and a respective second operand from the first and second series respectively. The instruction execution circuit selects the first and second series so they partially overlap. Positioning the operands is under program control.

Abstract: A data processing circuit has an execution circuit (18) with a plurality of functional units (20). An instruction decoder (17) is operable in a first and a second instruction mode. In the first instruction mode instructions have respective fields for controlling each of the functional units (20), and in the second instruction mode instructions control one functional unit. A mode control circuit (12) controls the selection of the instruction modes. In an embodiment, the instruction decoder uses time-stationary decoding of the selection of operations to be executed by the execution circuit (18) and the selection of destination registers from the set of registers (19). Mode switching is a more efficient way of reducing instruction time for time stationary processors than indicating functional units for which the instruction contains commands.

Abstract: A data processing circuit contains an instruction execution circuit that has an instruction set that comprises a SIMD instruction. The instruction execution circuit comprises a plurality of arithmetic circuits, arranged to perform N respective identical operations in parallel in response to the SIMD instruction. The SIMD instruction defines selects a first one and a second one of the registers. The SIMD instruction defines a first and second series of N respective SIMD instruction operands of the SIMD instruction from the addressed registers. Each arithmetic circuit receives a respective first operand and a respective second operand from the first and second series respectively, when executing the SIMD instruction. The instruction execution circuit is arranged for selecting the first and second series so that they partially overlap. Preferably, the position of the operands of at least one the series is under program control, preferably under control of operand data.

Abstract: A multimode accessible storage facility (10) is described that allows block access in a block access mode and row access in a row access mode. The facility comprises—a memory unit (20) comprising a plurality of memory banks (20.0, . . . , 20.F) each having a respective bank index (0, . . . , F), —an address generator (30) for generating for each of said memory banks a rotated bank address as a function of an input address and a shift parameter, —an input vector data rotator (40) for rotating an input vector and for providing vector elements of the rotated input vector to a respective bank of the memory unit, and —an output vector rotator (50) for inverse rotating a vector comprising vector elements retrieved from respective banks of the memory unit and for providing the rotated output vector.

Abstract: An image processing device comprising a synchronization unit (25) for generating a luminance (Y?) from the sum of pixel signals R, Gr, Gb, B, for subtracting the R pixel signal and the B pixel signal from the sum of the Gr pixel signal and Gb pixel signal so as to generate a first color difference (C1), and for calculating a difference between the R pixel signal and the B pixel signal to generate a second color difference (C2), a pseudo-color suppression unit (31) for performing pseudo-color suppression of the first color difference (C1) and/or the second color difference (C2), a color space conversion unit (37) for converting the luminance Y?, the first color difference (C1), the second color difference (C2), into a predetermined color space to generate YUV color information.

Abstract: A programmable signal processing circuit is used to (de-)interleave a data stream. Data from the signal stream is stored in a data memory (28) and read in a different sequence. The programmable signal processing circuit is used for computing addresses, for use in said storing and/or reading. The programmable signal processing circuit has an instruction set that contains an instruction to compute the addresses from preceding addresses that have been used for said storing and/or reading. In response to the instruction the programmable signal processing circuit permutes positions of a plurality of bits from the old address operand and forms of a bit of the new address result as a logic function of a combination of bits from the old address operand. Successive addresses are formed by means of repeated execution of a program loop that contains an address update instruction for computing the addresses.

Abstract: A processing apparatus is arranged to execute multiple-instruction words, a multiple-instruction word having a plurality of instructions. The processing apparatus comprises a plurality of issue slots (IS1, IS2) arranged for parallel execution of the plurality of instructions; a register file (RF1, RF2) accessible by the plurality of issue slots, and a communication network (CN) for coupling of the plurality of issue slots and the register file. The processing apparatus is further arranged to produce a first identifier (OV1) on the validity of first result data (RD1) produced by a first issue slot (IS1) and a second identifier (OV2) on the validity of second result data (RD2) produced by a second issue slot (IS2). The communication network comprises at least one selection circuit (SC1) arranged to dynamically control the transfer of either the first result data or the second result data to a register of the register file, in a single processor cycle, by using the first identifier and the second identifier.

Abstract: A computer system with a processing unit and a memory. The processing unit is arranged to fetch memory lines from the memory and execute instructions from the memory lines. Each memory line is fetched as a whole and is capable of holding more than one instruction. An instruction comprises information that signals explicitly how the processing unit, when processing the instruction from a current memory line, should control how a part of processing is affected by crossing of a boundary to a subsequent memory line. The processing unit responds to the information by controlling said part as signaled by the information.

Abstract: A programmable signal processing circuit has an instruction processing circuit (23, 24, 26), with an instruction set that comprises a depuncture instruction. The instruction processing circuit (23, 24, 26) forms the depuncture result by copying bit metrics from a bit metrics operand and inserting one or more predetermined bit metric values between the bit metrics from the bit metric operand in the depuncture result. The instruction processing circuit (23, 24, 26) changes the relative locations of the copied bit metrics with respect to each other in the depuncture result as compared to the relative locations of the copied bit metrics with respect to each other in the bit metric operand, to an extent needed for accommodating the inserted predetermined bit metric value or values.

Abstract: An image processing device, an image processing method, and an image processing program by which deformation such as distortion caused by an imaging optical system can be corrected with high precision without increase in memory capacity and processing time.

Abstract: A processing system according to the invention comprises a plurality of processing elements (PE1, . . . , PE7). The processing elements comprise a controller and computation means. The plurality of processing elements is dynamically reconfigurable as mutually independently operating task units (TU1, TU2, TU3), which task units comprise one processing element (PE7) or a cluster of two or more processing elements (PE3, PE4, PE5, PE6). The processing elements within a cluster are arranged to execute instructions under a common thread of program control. In this way the processing system is capable of using the same sub-set of data-path elements to exploit instruction level parallelism or task level parallelism or a combination thereof, dependent on the application.

Abstract: An image processing device includes: a coordinate conversion unit (142) which calculates a corresponding sampling coordinate on a color mosaic image corresponding to a pixel position of a color image when a deformation process is performed, according to the pixel position of the color image; a sampling unit (143); a sampling unit (143) which interpolates-generates a pixel value in a sampling coordinate for each of color planes obtained by decomposing the color mosaic image; and a color generation unit (144) which generates a color image by synthesizing interpolation values of the respective color planes. Each pixel value of a color image subjected to a deformation process is obtained as a pixel value of the sampling coordinate from the color mosaic image by interpolation calculation, thereby realizing the color interpolation process for generating a color image from the color mosaic image and a deformation process of the color image by one interpolation calculation.

Abstract: A data processing circuit has an execution circuit (18) with a plurality of functional units (20). An instruction decoder (17) is operable in a first and a second instruction mode. In the first instruction mode instructions have respective fields for controlling each of the functional units (20), and in the second instruction mode instructions control one functional unit. A mode control circuit (12) controls the selection of the instruction modes. In an embodiment, the instruction decoder uses time-stationary decoding of the selection of operations to be executed by the execution circuit (18) and the selection of destination registers from the set of registers (19). Mode switching is a more efficient way of reducing instruction time for time stationary processors than indicating functional units for which the instruction contains commands.

Abstract: A data processing circuit has a programmable processor (12a, b) with an instruction set that comprises an new type of instruction. This instruction has a first operand that refers to a string of bits, and a second operand that refers to a position in that string of bits. The programmable processor (12a, b) is arranged to execute this type of instruction by returning, as a result, a code that is indicative of a count of a number of bits that occurs from said position in the string of bits until the string of bits from said position deviates from a predetermined bit pattern. The instruction is particularly useful for use in programs that perform variable length decoding and/or decoding.