Abstract: A core logic circuit which works with a CPU and a main graphics accelerator in a computer system is provided. The core logic chip includes a host controller electrically connected to the CPU for receiving a command from the CPU; an auxiliary graphing engine electrically connected to the host controller for receiving and processing the command; and a transmission controller electrically connected to the auxiliary graphing engine for transmitting the command that is processed and outputted by the auxiliary graphing engine to the main graphics accelerator to be further processed.