Abstract: An apparatus and method for multiplying frequency of a clock signal are provided, wherein the apparatus provides an initial oscillator signal, compares the initial oscillator signal with a reference signal to generate a first control signal, selectively outputs one of at least one lower threshold value and at least one upper threshold value from a threshold value generation circuit to a clock output circuit according to at least the first control signal, and updates an output clock signal through a digital and logical module processing the comparison of the initial oscillator signal and the selected one of the at least one upper and lower threshold values and the comparison of the initial oscillator signal and a low level signal.

Abstract: A method of mode detection for OFDM signals. The method comprises the steps of delaying the OFDM signal for a first and second number of samples, multiplying the two delayed signals by coefficient signals, and deriving a sum of the two products, deriving an error signal by subtracting the sum of the two products from the OFDM signal, extracting amplitudes of the coefficient signals, and accordingly deriving step size signals, updating the coefficient signals according to the error signal and step size signals, detecting edges of the amplitudes of the coefficient signals, and determining the guard interval length and transmission mode according to the detected edges.

Abstract: The invention relates to an ESD protection with ability to enhance trigger-on speed of a low voltage Triggered PNP (LVTPNP) unit for protecting internal circuits of an integrated circuit from attack of an ESD stress. The ESD protection unit incorporates either detection circuit or power clamp circuit to efficiently trigger on a trigger node as a heavily doped region of LVTPNP devices among an I/O pad, a VDD pin and a VSS pin. As soon as the trigger node of each LVTPNP device receives a trigger signal from either the ESD detection circuit or power clamp circuit, the threshold voltage of the LVTPNP devices are capable of being therefore reduced to enhance trigger-on speed of the LVTPNP devices that discharge ESD current.

Abstract: A personal computer (PC) main board is used for mounting therein a memory module, and the memory module is capable of mounting therein one selected from a first type of Dynamic Random Access Memory (DRAM) and a second type of DRAM. The PC main board includes a memory module slot for replacably inserting therein the memory module and providing an operation voltage thereto, a switch device electrically connected to the memory module slot for changing a switching mode to adjust the operation voltage and an electric interface mode of the memory module in response to the type of the memory module, and a chipset electrically connected to the memory module slot and the switch device for switching operation modes between the first type of DRAM and the second type of DRAM in response to the switching mode of the switch device.

Abstract: A signal transmission device adapted to transmit an n-bit parallel digital signal is used for avoiding a transmission error. The device includes a detector for receiving a first and a second n-bit digital data consecutively occurred in the n-bit parallel digital signal, proceeding a first calculation to obtain a changed value, and outputting an indicating signal while the changed value is larger than a threshold, an encoder electrically connected to the detector for receiving the indicating signal and the second n-bit digital data, proceeding a second calculation, and outputting an encoded second n-bit digital data to reduce the changed value between the first n-bit digital data and the encoded second n-bit digital data below the threshold, and a decoder electrically connected to the detector and the encoder receiving the indicating signal and the encoded second n-bit digital data, proceeding a third calculation, and recovering the second n-bit digital data.

Abstract: A method of forming shallow trench isolation in a semiconductor substrate. A hard mask having an opening is formed on the semiconductor substrate. The semiconductor substrate is etched through the opening to form a shallow trench. The semiconductor substrate is annealed in an ambient containing argon gas at a temperature of about 1150 to about 1200° C. for 1 to 2 hrs. An insulator is then formed on the hard mask to fill the shallow trench. The insulator is planarized while the hard mask is used as the polishing stop layer. Thereafter, the hard mask is removed to expose the upper surface of the semiconductor substrate and leave a shallow trench isolation.

Abstract: The present invention relates to a quasi-synchronous multi-stage event synchronization apparatus by a phase lock loop (PLL) control circuit and a quasi-synchronous multi-stage synchronizer to tolerate clock uncertainty and speed up the synchronizing process between the asynchronous digital circuits from producing-end to consuming-end in the computer system. The phase lock loop (PLL) control circuit generates a pair of well-controlled clocks, PDU_CLK, CSM_CLK, assigned to producing-end and consuming-end and a pair of clock phase indicating signals, PDU_SYNC_PULSE, CSM_SYNC_PULSE, associated with the pair of well-controlled clocks. The quasi-synchronous multi-stage synchronizer routes the series of sync events into a synchronization stage with minimal synchronization delay from producing-end to consuming-end.

Abstract: A current output circuit for use in a digital-to-analog converter is disclosed. The current output circuit includes a current source for providing a driving current, and a first output circuit coupled with the current source. The first output circuit includes a first metal-oxide semiconductor (MOS) transistor device having a source electrode thereof connected to the current source in series, a first voltage amplifier coupled between the source electrode and a gate electrode of the first MOS transistor device for keeping a voltage of the source electrode substantially constant, and a first controlled switch coupled between an operational voltage and the gate electrode of the first MOS transistor device for being switched ON or OFF in response to a first digital control signal, and allowing the driving current to be outputted from a drain electrode of the MOS transistor device when the first controlled switch is switched ON.

Abstract: A method and a computer system are provided for using a portion of a local memory of a graphics card as an extensive memory of a system memory. When the computer system is rebooted, a portion of a local memory of a graphics card is claimed as an extensive memory of the system memory, and the local memory excluding the extensive memory is claimed a new local memory by a driver of the graphics card. The driver of the graphics card reports the new local memory capacity to an operating system of the computer. Then, a new system memory capacity including the extensive memory and the original system memory is claimed by a chipset of the computer system and reported to a memory sizing command of BIOS. Finally, if a memory access request is within the address range of the extensive memory, the memory access request is transmitted to the graphics card through AGP/PCI bus.

Abstract: A core logic circuit for use with a CPU and a main graphics accelerator in a computer system is provided. The core logic chip includes a host controller electrically connected to the CPU for receiving a command from the CPU; an auxiliary graphing engine electrically connected to the host controller fore receiving and processing the command; and a transmission controller electrically connected to the auxiliary graphing engine for transmitting the command processed and outputted by the auxiliary graphing engine to the main graphics accelerator to be further processed.

Abstract: A method for asserting signals onto an output line connected to a passive external pull-up resistor by using a fast edge rate signal driver is provided. The fast edge rate signal driver has first, second and third pull-down predrivers, first, second and third pull-up predrivers, first and second delay elements, and first, second and third output devices, and a PMOS and an NMOS current controller, and each of the output devices has one output terminal coupled to each other forming the output line.