Abstract: A touch control system includes: a touch panel; an active pen having a plurality of functions, the functions being used for controlling the active pen or the touch panel and initiated only by at least one voice signal, the active pen including: a voice receiving module configured to receive the at least one voice signal; a voice analyzing module configured to analyze the at least one voice signal to generate a controlling command; and a control module configured to determine that the controlling command is configured to control the active pen or the touch panel; and a touch controller electrically connected to the touch panel and receive, in response to the controlling command being configured to control the touch panel, the controlling command.

Abstract: A touch control system includes: a touch panel; an active pen having a plurality of functions, the functions being used for controlling the active pen or the touch panel and initiated only by at least one voice signal, the active pen including: a voice receiving module configured to receive the at least one voice signal; a voice analyzing module configured to analyze the at least one voice signal to generate a controlling command; and a control module configured to determine that the controlling command is configured to control the active pen or the touch panel; and a touch controller electrically connected to the touch panel and receive, in response to the controlling command being configured to control the touch panel, the controlling command.

Abstract: The method and apparatus use two inequalities to determine whether an estimated value obtained from conventional method and a correct value obtained from ideal conversion is identical. When those values are the same, the estimated value is not corrected; otherwise, according to the difference between those values, one is added or subtracted from the estimated value to obtain the correct result.

Abstract: A squelch circuit for operating at high speed and at high frequencies includes a squelch input unit, a low swing pre-amplifier and a sampling and decision circuit. The squelch input unit pre-processes the positive and negative signals of an input signal to generate four pre-processed signals that are paired and sent to the low swing pre-amplifier. The outputs of the low-swing pre-amplifier are then over-sampled by the sampling and decision circuit. Multi-phase clocks are used to control the over-sampling in the sampling and decision circuit. A logic circuit then determines if the state of the input signal based on multiple samples.

Abstract: A method for analyzing power noise and method for reducing the same are disclosed, wherein the present invention is utilized in an IC design process. First, a DC analysis is performed with a related IC design by utilizing computer aided design (CAD) software and circuit simulation software for obtaining a power network model of the IC design. Then, the power network model is defined as being composed of a plurality of unit blocks. After analysis, the quantity and type, etc., of components connected electrically to each of the unit blocks are recognized and are regarded as component reference data of each of the unit blocks. Afterwards, according to the component reference data of each of the unit blocks, the voltage drop (IR drop) occurring in operation for each of the unit blocks is evaluated and obtained by utilizing an equivalent circuit constructed by components that are connected electrically to each of the unit blocks.

Abstract: The present invention discloses a multiple-stage FIFO mechanism capable of receiving data signals correctly. The circuit includes a write-enable pulse sequencer for sequentially generating a plurality of write-enable signals. An N-stage FIFO sequentially stores an input data and outputs the input data. An output stage selector sequentially generates a control signal. And a multiplexer selectively outputs the input data from the N-stage FIFO.

Abstract: A method for removing noise regions in a stereo 3D image, which includes a first eye image and a second eye image is achieved by calculating a maximum offset value and turning a horizontal synchronization signal and a display enable signal of the CRT timing parameters.

Abstract: An aligned clock forwarding scheme of an electronic system includes a first circuit path generating an aligned clock output signal to a subsystem and a second circuit path generating an aligned data signal to the subsystem. An external clock input serves as the source of the clock signal for the aligned clock forwarding scheme. A multiplication circuit receives the external clock input and sends multiplied clock signals to control the first and second circuit paths. The two circuit paths have the same physical characteristics so that both clock output and data signals experience the same environmental effect. There is no additional skew incurred between the clock and data signals during the data transfer between the two subsystems.

Abstract: A differential phase discriminator includes a phase compensation circuit to compensate for timing drift and error for recovering timing information in a digital phase lock loop. The differential phase discriminator uses a differential phase detector to compute the phase difference of two consecutive frequency domain signal samples. The phase compensation circuit determines a phase correction term by computing the difference between the absolute values of the real and imaginary parts of a frequency domain signal sample. A weighting factor is computed by adjusting the sum of the absolute values of the real and imaginary parts of the frequency domain signal sample with a ratio adjustment factor. A phase compensation value is then computed by multiplying the phase correction term by the weighting factor. The phase compensation value is added to the uncorrected output of the differential phase detector.

Abstract: A method and an apparatus are provided in this invention to select an optimal swapping technique in discrete multi-tone system. The algorithm for performing gain-swapping is also proposed in the present invention. A swapping technique is selected from gain-swapping and a combination of bit-swapping and gain-swapping based on two index values such that the difference between the maximum mean square error (MSEmax) and the minimum mean square error (MSEmin) is minimized and the gain factor constraints are met. The first index value I is representative of range of improvement when adopting the gain-swapping as the swapping technique, and the second index value J is representative of range of improvement when adopting a combination of the gain-swapping and the bit-swapping as the swapping technique.

Abstract: An apparatus and method for pixel color enhancement are provided. The preferred embodiment includes a first circuitry, a second circuitry, a third circuitry, a fourth circuitry. In a preferred embodiment, the apparatus further includes a fifth circuitry. The first circuitry determines and outputs a reference value X. The second circuitry inputs the X, and (R, G, B) and subtracts X from three components (R, G, B) respectively to obtain values of (R?X), (G?X) and (B?X). The third circuitry inputs values of (R?X), (G?X) and (B?X) and scale values of (R?X), (G?X) and (B?X) by a factor S to generate values of S*(R?X), S*(G?X) and S*(B?X). The fourth circuitry 16 respectively adds values of S*(R?X), S*(G?X) and S*(B?X) to three components (R, G, B) to generate three enhanced components (R?, G?, B?).

Abstract: The present invention relates to a device for protecting high frequency RF integrated circuits from ESD damage. The device comprises at least one varactor-LC circuit tank stacked to avoid the power gain loss by the parasitic capacitance of ESD circuit. The varactor-LC tank could be designed to resonate at the RF operating frequency to avoid the power gain loss from the parasitic capacitance of ESD circuit. Multiple LC-tanks could be stacked for further reduction in the power gain loss. A reverse-biased diode is used as the varactor for both purposes of impedance matching and effective ESD current discharging. Because the inductor is made of metal, both the inductor and the varactor can discharge ESD current when ESD condition happens. It has a high enough ESD level to prevent ESD discharge.

Abstract: A mechanism for maintaining the first-in first-out order of commands in a multiple-input and multiple-output buffer structure includes a command number generator for generating and assigning a command number to each command entering the buffer structure, and a command number comparator for comparing the command number of the outgoing command at each buffer in the buffer structure to determine which command should exit. Both command number generator and command comparator have a cyclic counter that has a period greater than or equal to the total number of allowable buffer entries in the buffer structure. For maintaining order of posted and non-posted command queues, a pending posted write counter is used in the posted command queue to record the number of pending posted write command and each entry in the non-posted command queue is associated with a dependency counter.

Abstract: A process via mismatch detecting device is disclosed. Because the vias in the detecting circuit of process via mismatch detecting device are mismatched while the vias between the metal layers of the chips are mismatched, by appropriately placing vias in detecting circuit of process via mismatch detecting device properly, metal lines of different metal layers in the detecting circuit can become short-circuited by mismatched vias, so as to output a voltage signal that is higher after vias mismatch and is regarded as the result of detecting via mismatch. Therefore, the direction and quantity of via mismatch between the metal layers in the chip are detected and monitored effectively, so as to optimize the process. Thus, the yield of process is increased and the cost is decreased.

Abstract: Architecture of an efficient adaptive digital echo canceller includes a frequency domain update block, a far-end signal estimation block and a time domain echo cancellation block. The echo canceller has a training mode in which the frequency domain update block and far-end signal estimation block are first trained to estimate the echo channel and target channel. After the training mode, the time domain echo cancellation block uses the estimated echo channel to synthesize an echo replica and subtracted it from the received signal continuously before or in an operation mode. When a synchronization frame is received in the operation mode, the frequency domain update block and the far-end signal estimation block are used to retune both echo channel and target channel for improving system performance.

Abstract: A method for preventing reworked photoresist from collapsing is described. After stripping undesired photoresist off a wafer and before re-performing a lithography process thereon, the wafer is placed in a chemical vapor deposition chamber filled with N2O gas for a predetermined time to form a nitrogen-rich native oxide layer on the surface of the wafer. Afterwards, reworked photoresist is formed on the nitrogen-rich native oxide layer. The nitrogen-rich native oxide layer restores the moisture and the reflectivity of the surface of the wafer to a predetermined range before performing the photoresist reworking process. Hence, the invention prevents the reworked photoresist from collapsing and improves the fabrication yield.

Abstract: A memory address remapping method is disclosed. The memory address remapping method comprises: providing a cache-related address having a tag, an associative tag, a set index and a block offset; providing a linear operator; performing a linear calculation with a first linear operator input and a second linear operator input to obtain a first output, wherein the first linear operator input is several bits picked from the set index of the cache-related address according to a quantity and a corresponding location of a plurality of bits in the location address of a memory address, such as DDR memory-related address, Rambus memory-related address, etc.

Abstract: An equalization method and device for equalizing the received vestigial sideband (VSB) signal, utilizes segment-sync symbols, Sato directions, erasure slicers, and variable step-sizes. In addition to stop-and-go (SAG) mode, the directions of Sato errors can also be used for speed up the convergence of tap weights of the equalizer. Erasure slicers can mitigate the effect of decision errors as they are passed through the feedback filter. In time-variant environments, variable step-sizes help the equalizer tracking the variations of the channels; in time-invariant environments, variable step-sizes help ease the fluctuations of the steady-state equalizer tap weights, and therefore yield smaller mean-squared-error and better symbol error rate (SER).

Abstract: A memory read/write arbitration method is disclosed. The memory read/write arbitration method, which is utilized in a memory controller for increasing row hit rate and decreasing the delay of memory access, comprises: providing a arbitrator; providing a read request fifo queue having command read requests; providing a write request fifo queue having command write requests; performing a judgment step for generating a priority, wherein the judgment step comprises: performing a first sub-judgment step to determine that a command read request of the command read requests has priority over a command write request of the command write requests, or the command write request can be forwarded to a second sub-judgment step under adaptive first-step conditions; performing the second sub-judgment step to determine the read request has priority over the command write request from the first sub-judgment step, or the command write request from the first sub-judgment has priority over the command read request.

Abstract: A multi-layered substrate having built-in capacitors is disclosed. The substrate comprises at least one high permittivity of dielectric material filled in the through holes between the power plane and the ground plane so as to form capacitors. The built in capacitors are to decouple high frequency noise due to the voltage fluctuation.