Patents Assigned to Silicon Intergrated Systems Corp.
  • Patent number: 10141897
    Abstract: A source follower includes a first transistor, a first output module, a second transistor, a second output module and a feedback module. The first terminal and the control terminal of the first transistor are configured to respectively receive a first base voltage and a first control voltage. The second terminal of the first transistor and the first output module are electrically connected to a first output terminal. The first terminal and the control terminal of the second transistor are configured to respectively receive a first base voltage and a second control voltage. The second terminal of the second transistor and the second output module are electrically connected to a second output terminal. The feedback module is electrically connected to the control terminal of the first transistor, the control terminal of the second transistor and a reference node of the second output module.
    Type: Grant
    Filed: December 4, 2017
    Date of Patent: November 27, 2018
    Assignee: SILICON INTERGRATED SYSTEMS CORP.
    Inventors: Ssu-Che Yang, Wen-Chi Lin, Keng-Nan Chen
  • Patent number: 8907905
    Abstract: A sensing device placed in a touch sensing system of a display device includes a selector, a sensing module, and a detection module for determining touch signals generated by the touch sensing system. The selector selects two of the touch signals according to at least one selection control signal. The sensing module comprises a first differential amplifier for comparing the selected touch signals and producing a first differential signal according to first control signals. According to second control signals, the detection module receives the first differential signal, generates an averaged sensing value and a reference value, and compares the averaged sensing value with the reference value to produce a second differential signal. Thereby, the touch sensing system uses the second differential signal to generate the first control signals and the second control signals to control the operation of the touch sensing system.
    Type: Grant
    Filed: December 16, 2011
    Date of Patent: December 9, 2014
    Assignee: Silicon Intergrated Systems Corp.
    Inventors: Song Sheng Lin, Ssu-Wei Chang, Ying-Jyh Yeh
  • Publication number: 20130114213
    Abstract: An electronic device having a base includes a circuit board, a electronic element, and a heat sink. The electronic element is mounted on the circuit board. The heat sink attaches to the electronic element. The heat sink includes an attaching wall and at least one side wall. The attaching wall attaches to the electronic element and having two opposite ends. At least one side wall connects to the ends of the attaching wall. The side wall and the attaching wall form a tube with an intake opening and an outtake opening. The intake opening faces the base and the outtake opening is opposite to the intake opening.
    Type: Application
    Filed: November 9, 2011
    Publication date: May 9, 2013
    Applicant: SILICON INTERGRATED SYSTEMS CORP.
    Inventors: Tsai-Chih Tsai, Yin-Chieh Hsueh, Shih-Ya Lin
  • Publication number: 20110285728
    Abstract: An image signal processing system is presented, which includes a computer, a master image processing device, and at least one slave image processing device. The master image processing device is used for receiving an image signal. The master image processing device includes a master signal conversion device and a master signal output device. The master signal conversion device is used for converting the image signal into an instruction signal, and the master signal output device is used for outputting the instruction signal. The slave image processing device includes a slave signal input device, a slave signal conversion device, and a GPU. The slave signal input device is used for receiving the instruction signal. The slave signal conversion device is used for selectively converting the instruction signal into an image signal according to the instruction signal. The GPU is used for receiving the image signal and generating a broadcasting signal.
    Type: Application
    Filed: December 3, 2010
    Publication date: November 24, 2011
    Applicant: SILICON INTERGRATED SYSTEMS CORP.
    Inventors: Ching Chang Shih, Kuan Yu Chen, Yen Yu Chen
  • Patent number: 7209354
    Abstract: The present invention provides a heat sink device for the package device to improve the heat dissipating efficiency. The heat sink device includes a first heat sink assembly and a second heat sink assembly. The first heat sink assembly has a first heat dissipating structure, a second heat dissipating structure positioned above first the heat dissipating structure, at least two thermal supports on the backside of the first heat sink assembly and a thermal block on the backside of the first heat sink assembly. The second heat sink assembly has a protruding structure and at least the openings. The first heat sink assembly is fixed with the second heat sink assembly to form a heat sink device by the combination of the thermal supports and the openings. The first heat sink assembly and the second heat sink assembly are attached to the integrated circuit device separately by the thermal block and the protruding structure.
    Type: Grant
    Filed: December 2, 2003
    Date of Patent: April 24, 2007
    Assignee: Silicon Intergrated Systems Corp.
    Inventors: Chung-Ju Wu, Wei-Feng Lin
  • Patent number: 7095784
    Abstract: A method and apparatus for rate control in moving picture compression. Bit allocation with initial quantization step size estimation is used at picture level. With the relationship between pre-analyzed activity of current picture to be encoded and actual complexity of previously encoded picture of the same type, a target bit budget can be allocated to the current picture in accordance with the present invention. Once the target bit budget has been determined, an initial value for an average quantization step size is estimated on the basis of the target bit budget, along with the relationship between pre-analyzed activity of current picture and actual complexity of previously coded picture. Such an initial value of the average quantization step size is useful to achieve higher picture quality at a given bit allocation.
    Type: Grant
    Filed: April 14, 2003
    Date of Patent: August 22, 2006
    Assignee: Silicon Intergrated Systems Corp.
    Inventors: Yung-Ching Chang, Chia-Chieh Chen, Teng-Kai Wang
  • Patent number: 7049659
    Abstract: A method of manufacturing a semiconductor device having a first and second transistor of an ESD protection and internal circuit respectively. The method includes the steps of providing a substrate, forming gates of the first and second transistor on the substrate, depositing a mask layer and patterning the mask layer using one single mask to remove the mask layer on the gates, a portion of a drain region of the first transistor, and a source and drain region of the second transistor, implementing ESD implantation under the regions without the patterned mask layer, removing the mask layer and forming sidewall spacers of the gates, and implementing drain diffusion.
    Type: Grant
    Filed: September 10, 2003
    Date of Patent: May 23, 2006
    Assignee: Silicon Intergrated Systems Corp.
    Inventors: Ming-Dou Ker, Hsin-Chyh Hsu, Wen-Yu Lo
  • Patent number: 6956964
    Abstract: An apparatus is provided to produce a real-time anaglyph, comprising a graphics engine, a memory and an anaglyph generator. The graphics engine provides a sync signal and generates a left eye image and a right eye image in accordance with a horizontal offset calculated from a 3D graphic animation, wherein the horizontal offset between the left and the right eye images creates illusion of depth. The left eye image and the right eye image are temporarily stored in the memory. The anaglyph generator then fetches the left eye image and the right eye image from the memory in response to the sync signal, for producing a filtered left image and a filtered right image. As such, each filtered image is respectively tinted with one of the complementary colors. By viewing through a pair of anaglyph glasses, the filtered left and the filtered right images can thus create perception of depth.
    Type: Grant
    Filed: November 8, 2001
    Date of Patent: October 18, 2005
    Assignee: Silicon Intergrated Systems Corp.
    Inventors: Ruen-Rone Lee, Hsi-Jou Deng, Chin Sung Lee
  • Patent number: 6690384
    Abstract: A system for full-scene anti-aliasing and stereo three-dimensional display control. The system includes a receiving buffer, a geometry offset generator, a rendering engine, and a blending engine. The receiving buffer receives a geometry, and the geometry offset generator receives stereo parameters and FSAA parameters, calculates first and second stereo offsets according to the stereo parameters, and calculates first and second FSAA offsets according to the FSAA parameters. The rendering engine combines the first and second stereo offsets with the first FSAA offset respectively to obtain first and second new offsets, combines the first and second stereo offsets with the second FSAA offset respectively to obtain third and fourth new offsets, and re-renders the geometry according to the first, second, third, and fourth new offsets respectively, so as to obtain first, second, third, and fourth new geometry.
    Type: Grant
    Filed: April 1, 2002
    Date of Patent: February 10, 2004
    Assignee: Silicon Intergrated Systems Corp.
    Inventors: Yung-Feng Chiu, Hsi-Jou Deng, Ruen-Rone Lee
  • Patent number: 6486059
    Abstract: A dual damascene process is applied on a semiconductor substrate having a dual damascene opening with a via hole which exposes a metal wire and is surrounded by a first low-k dielectric layer, and a trench which is over the via hole and surrounded by a second low-k dielectric layer. An in-situ oxide liner, serving as a dielectric barrier layer, is formed on the sidewall of the first low-k dielectric layer and the second low-k dielectric layer. A metal barrier layer is conformally deposited on the exposed surface of the semiconductor substrate to cover the sidewall and bottom of the dual damascene opening. The dual damascene opening is filled with a conductive layer, and then the excess conductive layer outside the trench level is polished away by a CMP process.
    Type: Grant
    Filed: April 19, 2001
    Date of Patent: November 26, 2002
    Assignee: Silicon Intergrated Systems Corp.
    Inventors: Shyh-Dar Lee, Chen-Chiu Hsue
  • Patent number: 6175659
    Abstract: In an image scaling method and apparatus that uses adaptive edge enhancement, a plurality of sets of gradient threshold values and enhancement threshold values correspond respectively to predetermined enhancement modes. The enhancement mode corresponding to a mean pixel value for a one-dimensional pixel array that includes a center pixel to be updated and neighboring pixels of the center pixel is determined so that one of the sets of gradient threshold values and enhancement threshold values corresponding to the selected enhancement mode can be selected. After a sharpness value is computed by adding together absolute values of differences between values of the center pixel and each of the neighboring pixels, one of the enhancement threshold values in the selected set is selected by comparing the sharpness value with the gradient threshold values in the selected set.
    Type: Grant
    Filed: October 6, 1998
    Date of Patent: January 16, 2001
    Assignee: Silicon Intergrated Systems Corp.
    Inventor: Chien-Hsiu Huang