Abstract: In a particular embodiment, a power sourcing equipment (PSE) device includes at least one network port adapted to couple to a powered device to provide power and optionally data to the powered device via a network cable. The PSE device further includes a current limiter circuit coupled to the at least one network port and having an adjustable threshold. The PSE device also includes a logic circuit coupled to the current limiter circuit and adapted to reduce the adjustable threshold of the current limiter circuit to have a threshold level that is below a nominal operating current level. After a period of time has elapsed during which the current limiter circuit is not activated, the logic circuit is adapted to determine that the powered device is disconnected from the at least one network port.

Abstract: A switched capacitor voltage reference including a single bias current source, three capacitors, diode devices, an amplifier and switching circuits for developing a temperature independent reference voltage. A single current source avoids having to match multiple current sources. A first capacitor and at least one diode device set a voltage having a negative temperature coefficient. A second capacitor and each of the diode devices set a voltage having a positive temperature coefficient. A third capacitor allows adjustable gain to enable a wide voltage range including a low voltage such as less than one volt. The switching circuits switch between multiple modes for developing and then combining the different temperature coefficient voltages. The topology allows a simple amplifier to be used. The topology is inherently accurate and does not require device trimming. An averaging method may be used to compensate for any mismatch between the diode devices.

Abstract: On-chip decoupling capacitors and methods for placing the same are disclosed in which designated spaces are created between the active circuits to insert designated capacitor cells. The designated capacitor cells may be placed in designated areas of the integrated circuit that are not simply spaces left empty by cell placement or frontier areas in or around the route, and the dimensions (e.g., height) of the designated capacitor cells may be selected to optimize (increase) capacitance efficiency. The capacitor cells may also be placed to target and reduce the interference between a digital core (aggressor) circuit and a victim analog circuit.

Abstract: An integrated circuit receives a first and second clock signal and a select signal that selects one of the clock signals. A glitchless switching circuit supplies an output clock signal according to which of the first and second clocks is selected by the select signal. A reset circuit coupled to the glitchless switching circuit responds to a direction of a transition of the select signal and generates a first reset signal in response to a first direction of the transition and generates a second reset signal in response to a second direction of the transition. The reset pulses are supplied respectively to first and second paths in the glitchless switching circuit to reset the state machine formed by the first and second paths in the event one of the input clocks is absent.

Abstract: A technique includes selectively enabling a first sequence of unit elements of a plurality of unit elements of a digital-to-analog converter to convert a digital code to a plurality of analog signals in response to a plurality of control signals. Individual control signals of the plurality of control signals and individual analog signals of the plurality of analog signals correspond to respective unit elements of the plurality of unit elements. The technique includes generating the plurality of control signals based on the digital code, a random digital code having a number of bits based on a feedback signal, and an indicator of a second sequence of unit elements of the plurality of unit elements enabled in response to a prior digital code.

Abstract: A transmitter is adapted to be programmed to select an amplifier operating class for the transmitter out of a plurality of amplifier operating classes. The transmitter is also adapted to operate according to the selected amplifier operating class to communicate a signal to an antenna.

Abstract: A receiver includes an input section, a plurality of RF sections, an output circuit, and a controller. The input section receives and amplifies a radio frequency (RF) input signal to provide an amplified RF signal, and has a gain input. The plurality of RF sections each have an input for receiving the amplified RF signal, and an output for providing an intermediate frequency signal. The output circuit provides an intermediate frequency output signal in response to an output of at least one of the plurality of RF sections. The controller has an output coupled to the gain input of the input section.

Abstract: An apparatus includes a housing having a front surface, a rear surface, and at least one sidewall therebetween and a plurality of optical windows formed in the housing to allow light to pass through from multiple directions. The apparatus further includes a plurality of photo detectors to generate electrical signals based on received light, where each of the plurality of photo detectors is disposed within a respective one of the plurality of optical windows. The apparatus also includes a control circuit coupled to the plurality of photo detectors to receive the electrical signals, determine light variations from the electrical signals, and determine a change in position of an object based on variation ratios of the light variations received by at least one pair of photo detectors within the plurality of photo detectors in response to determining the light variations.

Abstract: Systems and methods for handling data rate changes within a packet or frame are described. In an embodiment, a system may include a radio frequency (RF) circuit operable to receive a message having a plurality of segments, including a first segment that is modulated according to a first modulation data rate. The system may also include a demodulator circuit coupled to the RF circuit and operable to demodulate the first segment into a first demodulated segment having a demodulation data rate, wherein the demodulation data rate is greater than the first modulation data rate. The system may further include a de-mapper circuit coupled to the demodulator circuit and operable to convert the first demodulated segment into a first converted segment having the first modulation data rate.

Abstract: Systems and methods for a digital-to-charge converter (“DQC”) are disclosed. A DQC may include a converting circuit configured to receive a first digital signal indicative of a voltage across a capacitor coupled to an output pin of the digital-to-charge converter and to determine a present charge of the capacitor based at least in part on the first digital signal. The DQC may also include an error determining circuit coupled to the converting circuit, wherein the error determining circuit is configured to receive a second digital signal indicative of a target charge via an input pin of the digital-to-charge converter and to determine a difference between the target charge and the present charge. The DQC may further include a correction circuit coupled to the error determining circuit and configured to control a programmable current source to produce an analog signal at the output pin in response to the determined difference.

Abstract: Pop/clock noise reduction circuitry is disclosed for audio output circuitry. After audio output circuitry is enabled, reference voltage generator circuitry is then enabled to produce a reference voltage that ramps from a first voltage level to a second voltage level at a smooth rate. The ramping reference voltage is applied to the input of the audio output circuitry to reduce or prevent pop/click noise for the audio output circuitry. Further, negative offset control circuitry can also be used to provide a negative offset input to the audio output circuitry to remove initial step-up voltage levels that may exist at operational power-up for the audio output circuitry. Still further, current control circuitry can also be used that limits the available current flowing to the output node for the audio output circuitry, thereby further reducing and/or preventing potential pop/click noise in the audio output signals.

Abstract: Gas sensor materials and methods are disclosed for preparing and using the same to produce gas sensor structures. Also disclosed are gas sensor structures and systems that employ these disclosed materials. A gas sense-enhancing metal such as platinum may be added to a gas sensitive metal oxide material in a manner that more highly disperses the added platinum than conventional methods so as to more effectively utilize the platinum at a lower concentration, thus achieving a more cost effective solution. An ink vehicle may also be used for deposition of a gas sensitive material (e.g. on the surface of integrated circuit) that is formulated to allow “burn-out” of ink vehicle components at relatively low temperatures as compared to conventional ink vehicles.

Abstract: A flexible clock synthesizer technique includes generating a phase interpolator calibration signal to adjust a phase interpolator output signal generated by a phase interpolator of an interpolative divider. The phase interpolator is responsive to a phase interpolator control code and an output signal of a fractional-N divider of the interpolative divider. The phase interpolator calibration signal is based on an error signal indicative of a phase interpolator error. The error signal may indicate a phase relationship between a reference clock signal and a feedback clock signal of a PLL. The interpolative divider may be coupled in a feedback path of the PLL. The PLL may receive a reference clock signal and the feedback clock signal may be an adjusted phase interpolator output signal. The phase interpolator calibration signal may be a phase interpolator offset code corresponding to the phase interpolator control code or a phase interpolator gain signal.

Abstract: Systems and methods are disclosed for time-domain diversity combining of radio frequency (RF) broadcast signals. Two channelized quadrature (I/Q) signals are generated by different tuner circuitry coupled to two different antennas, are converted to frequency-domain signals, and are used to generate frequency-domain diversity weighting signals. The frequency-domain diversity weighting signals are then converted to time-domain weights and applied to the channelized I/Q signals. The weighted and channelized I/Q signals are then combined in the time-domain to provide a time-domain diversity combined signal. The resulting combined signal can be further processed, as desired, such as by using a demodulator to generate demodulated output signals. Disclosed methods and systems can be applied to a variety of receiver systems configured to receive RF broadcast signals.

Abstract: An integrated circuit (IC) having a radio receiver configured to perform a jitter self-test is disclosed. In one embodiment, an IC includes a radio receiver and a pulse generator. The pulse generator is configured to generate a pulse train based on a first periodic signal received from the radio receiver. The radio receiver is configured to use the pulse train to determine an amount of phase noise generated by a local oscillator of the radio receiver. The pulse generator and the radio receiver are implemented on the same IC die.

Abstract: An apparatus and a method for compensating for a mismatch in temperature coefficients of two oscillator frequencies to match a desired frequency ratio between the two oscillator frequencies over a temperature range. In one embodiment of a temperature sensor, first and second oscillators of different temperature characteristics are coupled to a differential frequency discriminator (DFD) circuit. The DFD circuit compensates for the different characteristics in order to match a frequency difference between the first and second frequencies over a temperature range.

Abstract: An input digital signal is converted to an analog signal using a main digital to analog converter (DAC) and a sub DAC. An offset value is subtracted from the input digital signal to generate an offset adjusted digital signal. The main DAC converts the offset adjusted digital signal to a first analog signal. A second digital signal is generated based on the offset value and a correction factor determined, at least in part, during calibration of the main DAC. The sub DAC converts the second digital to a second analog signal, which when combined with the first analog signal, provides an analog representation of the input digital signal.

Abstract: A converter in a radio-frequency (RF) apparatus includes a feedback circuitry. The feedback circuitry has a shielded input and a shielded output. The shielded input and the shielded output of the feedback circuitry tend to reduce interference in the converter.

Abstract: A microelectromechanical system (MEMS) device includes a resonator anchored to a substrate. The resonator includes a first strain gradient statically deflecting a released portion of the resonator in an out-of-plane direction with respect to the substrate. The resonator includes a first electrode anchored to the substrate. The first electrode includes a second strain gradient of a released portion of the first electrode. The first electrode is configured to electrostatically drive the resonator in a first mode that varies a relative amount of displacement between the resonator and the first electrode. The resonator may include a resonator anchor anchored to the substrate. The first electrode may include an electrode anchor anchored to the substrate in close proximity to the resonator anchor. The electrode anchor may be positioned relative to the resonator anchor to substantially decouple dynamic displacements of the resonator relative to the electrode from changes to the substrate.

Abstract: A system and method for generating an analog signal is disclosed. In one embodiment, system includes a first-in, first-out (FIFO) buffer configured to receive and store a plurality of digital values written to the FIFO buffer. The system further includes a digital-to-analog converter (DAC) coupled to read the digital values from the FIFO buffer and configured to convert the digital values to an analog signal. The FIFO buffer is configured to operate in a first mode in which writes to the FIFO buffer are inhibited and current digital values stored in the FIFO buffer are provided to the DAC in a repeating sequence.