Abstract: A circuit for protecting a battery includes an n-well formed within a p substrate. A p-type resistor is formed with in the n well and has a connection to the battery. An n+ ring is also formed in the n well and substantially surrounds the p-type resistor.

Abstract: Method and apparatus for calibration of a low frequency oscillator in a processor based system. A method for calibrating an on-chip non-precision oscillator. An on-chip precision oscillator is provided having a known frequency of operation that is within an acceptable operating tolerance. The on-chip precision oscillator is used as a time base and then the period of the on-chip oscillator is measured as a function of the time base. The difference between the measured frequency of the on-chip non-precision oscillator and a desired operating frequency of the on-chip non-precision oscillator is then determined. After the difference is determined, the frequency of the on-chip non-precision oscillator is adjusted to minimize the determined difference.

Abstract: A method for converting analog data to digital data is disclosed. The method includes operating an analog-to-digital data converter in a tracking mode to sample an input signal and in a convert mode to convert the sampled input signal after sampling to a digital signal. The analog-to-digital data converter is controlled with a controller to operate in different modes of operation by providing at least one step wherein the tracking mode of operation is controlled to initiate at a predetermined time to begin the sampling operation.

Abstract: DMA controller for mixed signal device. A mixed signal integrated circuit with memory control is disclosed. A data conversion circuit is provided that is operable to receive an analog input signal and convert discrete samples thereof at a predetermined sampling rate to a digital representations thereof as a plurality of digital words. A memory stores the digital words generated by the data conversion circuit. A processor is included on the integrated circuit and operable to access the memory to output select ones of the digital words for processing thereof in accordance with a predetermined processing algorithm. A memory access controller controls access to the memory by the data conversion circuit and the processor.

Abstract: A reconfigurable processor system n an intergrated circuit includes a processor core that operates on a set of instructions to carry out predefined processes. A plurality of input/output pins are provided for interfacing with external signals. A reconfigurable interface interfaces between the processor core and the input/output pins through select ones of a plurality of functional blocks. The reconfigurable interface is operable to define how each of the plurality of input/output pins interfaces with the processor core an the functionality associated therewith. The functional blocks provide the interface of the processor core with the input/output pins.

Abstract: A magnetic stripe card reader for reading a magnetic stripe on a card having at least one track of magnetically stored information stored thereon as a stream of encoded discrete data bits separated by bit times is disclosed. Aa magnetic head is provided for reading the magnetic pulses as the magnetic stripe is passed thereby to output a time varying analog signal. A data converter incorporated on an integrated circuit is then operable for converting the analog signal to a digital time series of digital values. A processor incorporated on the integrated circuit can ten process the digital output of the data converter and is operable to first determine potential bit boundaries and then recover timing information from the digital time series to discriminate the bit times between data bits. The value of each data bit is then determined during each bit time to provide a stream of extracted data bits.

Abstract: A capacitor structure in an integrated circuit includes a capacitor region defined within the boundaries thereof with an active circuit layer formed on the surface of the semiconductor substrate. A planarization layer is disposed over the active circuit layer and electrically isolated therefrom in at least the capacitor region. A metal capacitor layer is formed over the planarization layer within the capacitor region and having the bottom plates of a plurality of capacitors defined therein. A layer of dielectric is formed on the bottom plates of the plurality of capacitors of a predetermined thickness. A top plate is formed on the dielectric for each of the plurality of capacitors to define each of the plurality of capacitors, such that a portion of each of the bottom plates extends outside of the boundaries of the associated top plate.

Abstract: A voltage reference generator is disclosed that includes a current generator for generating a current that is proportional to absolute temperature (PTAT), the current generator having an internal resistance. This provides a PTAT current that is proportional to the resistance and wherein the temperature coefficient of the PTAT current is defined by the resistance. An output node is driven by the current generator with the PTAT current. A stack of serial connected MOS devices is connected between the output voltage and a ground reference voltage. The stack of transistors has a transimpedance associated therewith which has a temperature coefficient that is opposite in polarity to the temperature coefficient of the internal resistance and of a magnitude to provide a voltage on the output node that is substantially stable over temperature.

Abstract: A method is disclosed for converting DC power from a first voltage level on an input to a different voltage level on an output for delivery to a load. The method includes switching current in a switching operation from the input to the output through an inductive element and measuring the voltage/current parameters on the input and output. A control algorithm is then utilized to determine control parameters necessary to make a control move to effect the switching operation, the control algorithm utilizing as inputs the measured voltage/current parameters. A digital control system controls the switching operation, which digital control system is operable to be controlled by the control algorithm. Configuration data is received on a serial data bus for configuring the control algorithm. Thereafter, the operation of the control algorithm is modified in response to receiving the configuration information.

Abstract: A matrix of routing cells forming a cross-bar decoder (310). Signal triplets are coupled through the cross-bar decoder (310) based on control by a microprocessor. A register (50) provide control signals to the cross-bar decoder (310) to either activate or deactivate routing of the triplet signals through cells of the cross-bar decoder (310). The routing cells are arranged in a matrix of columns and rows. Each row of cells is associated with a common data signal input, and each column of the matrix is associated with a common I/O pin. The cells are individually enabled by the microprocessor so that any data signal can be coupled to any of the I/O pins. In addition to routing data signals through the cells, other signals are also routed through the cells.

Abstract: Open loop common mode driver for switched capacitor input to SAR. A method for controlling the operation of a SAR conversion cycle. The method includes the steps of first initiating the SAR conversion cycle by connecting one side of a plurality of capacitors in a capacitor array to a first capacitor reference voltage and the other side of the plurality of capacitors to the input of a comparator. This is followed by the step of sequentially switching in a plurality of compare cycles the one side of a select one or ones of the capacitors to a second capacitor reference voltage to change the voltage on the input of the comparator. Then, a compare operation is initiated after initiation of each compare cycle to compare the value on the input of the comparator with a compare reference voltage after a predetermined settling time has elapsed from the beginning of the initiation of each compare cycle.

Abstract: SAR with partial capacitor sampling to reduce parasitic capacitance. An analog-to-digital convertor is disclosed with reduced parasitic capacitance on the input during a sampling operation. A charge-redistribution, binary-weighted switched-capacitor array is included having a plurality of array capacitors that each have a commonly connected plate interfaced to a first common node and a switched plate, the switched plate operable to be switched between first and second reference voltages during a redistribution phase and select ones of the capacitors additionally operable to be switched to the input during a sampling phase. Each of the array capacitors has a parasitic capacitance associated therewith. A compensation capacitor having a common plate is connected to the first common node and a switched plate, the compensation capacitor operable to be switched to the input during the sampling phase and to the first reference voltage during the redistribution phase.

Abstract: Serial Data Interface. A method of serial communication is provided with an integrated circuit. The operation of the integrated circuit is first interrupted on at least one input/output associated with the operation of the integrated circuit. Serial data is then transmitted over the at least one input/output, the operation of which was interrupted, and during the interruption thereof.

Abstract: Method and apparatus for subclocking a SAR analog-to-digital converter. A method is disclosed for clocking the operation of a SAR analog-to-digital converter (ADC). A low frequency clock and a high frequency clock are provided. An analog input voltage is then tracked during a tracking phase to sample the value thereof. A conversion cycle referenced to an edge of the low frequency clock is then initiated. The sampled data is then converted in a conversion operation during a data conversion cycle, which conversion operation requires a plurality of conversion clock cycles, the timing of at least a portion of the conversion operation is controlled during the data conversion cycle utilizing the high frequency clock as the conversion clock.

Abstract: Open loop common mode driver for switched capacitor input to SAR. A method for selectively switching capacitors in a SAR capacitor array that have a common plate thereof interfaced to the input of a comparator. The method includes the step of first initiating a SAR compare cycle. Then. the other plates the capacitors switched such that they are disposed at either a first capacitor reference voltage or a second capacitor reference voltage in a combination and sequence of switching operations defined by a successive approximation search algorithm. Each switching operation in the sequence requires, after the step of switching, a comparison of the voltage input to the comparator with a compare reference voltage after a predetermined settling time from the time the capacitor combination for the switching operation has been switched. The duration of the settling time is controlled for each of the switching operations in the sequence such that at least two of the durations are different.

Abstract: Open loop common mode driver for switched capacitor input to SAR. A unity gain driver amplifier is disclosed for driving an output node that is connected to a capacitive load. The amplifier includes a first stage amplifier for driving an intermediate node, a positive voltage input node for being connected to an input voltage and a negative input node for receiving a feedback signal. A complimentary output stage is provided having an input connected to the intermediate node and an output connected to the output node, a voltage representative of the voltage on the output node fed back to the negative input of said first stage amplifier. Isolation circuitry then isolates the output node from the negative input node of the first stage amplifier as to phase shift due to large values of the capacitive loading during operation of the driver amplifier.

Abstract: Common centroid layout for parallel resistors in an amplifier with matched AC performance. An amplifier is disclosed that is formed on a silicon substrate that includes first and second differential legs, each driving first and second resistive loads. The first resistive load comprises first and second parallel resistive loads connected on one side thereof to one end of the first differential leg and the other side of each of the first and second parallel resistive loads separately connected to a first reference voltage. The second resistive load comprises third and fourth resistive loads each connected on one side thereof to one end of the second differential leg and the other side of each of the third and fourth parallel resistive loads connected separately to the first reference voltage. Each of the first, second, third and fourth resistive loads is fabricated of a strip of resistive material disposed on the surface of the substrate and having a finite resistivity, length, width and thickness.

Abstract: Noise cancellation in a single ended SAR converter. A single ended SAR converter front end is disclosed with common mode driver noise cancellation. The SAR converter front end includes a differential amplifier having positive and negative inputs and an output. A switched capacitor array is provided that is operable in a SAR data conversion operation to vary the voltage on one of the positive or negative inputs of the differential amplifier. A common mode driver drives a common mode node with a low impedance common mode voltage signal to a common mode node, and switching circuitry then switches the common mode voltage signal on the common mode node to the positive and negative inputs of the differential amplifier during a portion of a SAR data conversion cycle.

Abstract: Mixed signal processor with noise management. A method for noise management in a mixed signal processor integrated circuit having a digital processing section and an analog section The digital processing section is clocked at a first clock rate to process digital data. When a conversion operation is to be carried out by the analog section, the clocking of the digital processing section is inhibited during at least a portion of the data conversion operation by the analog section to prevent noise from clock transitions in the digital processing section from being injected into the analog section during the at least a portion of th data conversion operation.

Abstract: Method and apparatus for combining outputs of multiple DACs for increased bit resolution. A method for providing an increased bit resolution to a data converter operable to convert digital information to analog values. A first current Digital-to-Analog (IDAC) converter is controlled to provide current to a first output node, the first IDAC having a first current step size associated with the Least Significant Bit (LSB) thereof. A second IDAC is controlled to provide current to the first output node, the second IDAC having a second current step size associated with the LSB thereof that is smaller than the first current step size. The combination of the first and second IDACs increases the bit resolution of the first IDAC when driving the first output node with the second IDAC.