Abstract: An MRAM device is provided which includes an array of magnetic elements, a plurality of conductive lines configured to set magnetization states of the magnetic elements and circuitry configured to vary current applications along one or more of the conductive lines. In some cases, the MRAM device may additionally or alternatively include circuitry which is configured to terminate an application of current along one or more of the conductive lines before magnetization states of one or more magnetic elements selected for a write operation of the device are changed. In either case, a device is provided which includes an MRAM array and a first storage circuit comprising one or more magnetic elements, wherein the first storage circuit is configured to store parameter settings characterizing operations of the magnetic random access memory array within the magnetic elements. Methods for operating the devices provided herein are contemplated as well.

Abstract: Methods for patterning a magnetic cell junction and a topography used for and/or resulting from such methods are provided. In particular, a method is provided which includes etching portions of a topography adjacent to a patterned photoresist layer to a level within a cap film of the topography, removing etch residues from the topography and subsequently etching the remaining portions of the cap film to expose an uppermost magnetic layer. Another method is provided which includes patterning a dielectric mask layer above a patterned upper portion of a magnetic cell junction and ion milling a lower portion of the magnetic cell junction in alignment with the mask layer. An exemplary topography which may result and/or may be used for such methods includes a stack of layers having a dual layer cap film arranged above at least two magnetic layers spaced apart by a tunneling layer.

Abstract: A magnetic memory array with an improved word line configuration is provided. In some embodiments, the magnetic memory array may be adapted to selectively supply voltage from a single source line to one or more transistors arranged within a first row of the magnetic memory array and to one or more transistors arranged within a second row of the magnetic memory array. In addition or alternatively, the magnetic memory array may be configured to enable current flow along a single current path through a magnetic junction and along multiple paths extending from the single current path to a plurality of transistors. In some embodiments, the plurality of transistors may be formed from a contiguous conductive structure comprising the word line. In some cases, the word line may be configured to include at least two transistors that share a common diffusion region.

Abstract: A memory storage circuit is provided which includes a plurality of magnetic elements each configured to store bits in a first or a second logic state. The storage circuit may further include a plurality of transistors coupled to at least two of the magnetic elements. Such a plurality of transistors may be collectively configured to store bits in the first and second logic states as well. The memory storage circuit may include circuitry configured to load bits from a set of the magnetic elements into the plurality of transistors. Another circuit is provided which includes a magnetic element interposed between a bit line and an electrode. The circuit may further include a first set of circuitry configured to induce current flow through the magnetic element in a direction from the electrode to the bit line. A method for operating a memory storage circuit with the aforementioned configurations is also provided.

Abstract: A memory array configuration is provided that includes a plurality of magnetic cell junctions and a conductive line comprising a gate of a first transistor configured to enable a read operation for one of a plurality of magnetic cell junctions and a gate of a second transistor configured to enable a write operation for another of the plurality of magnetic cell junctions. Another memory array configuration is provided which includes a set of conductive structures serially coupled to a bit line spaced apart from and, in some embodiments, directly above a magnetic cell junction, a transistor coupled to the set of conductive structures and a program line collectively configured with the bit line to induce current flow through the set of conductive structures upon an application of a voltage to a gate of the transistor. A method for operating such a magnetic memory array is also contemplated herein.

Abstract: A memory cell includes a magnetic cell junction having an antiferromagnetic layer within a portion of the cell junction that is adapted to characterize a logic state of a bit written to the junction. More specifically, a memory cell includes, an antiferromagnetic layer arranged in contact with an adjacent magnetic layer within a storing portion of a magnetic cell junction. Such a magnetic cell junction configuration and a method for programming a memory cell with such a cell junction configuration may be used to improve the write selectivity of a memory cell array and reduce the amount of current needed to write a bit to a memory cell. Moreover, a memory cell includes a magnetic cell junction having an aspect ratio less than 1.6. In addition, a memory cell includes at least two resistors.

Abstract: A method is provided which includes patterning one or more metal layers arranged above a metal insulating layer and terminating the patterning process upon exposure of the metal insulating layer. In particular, the method may be adapted to be more selective to the metal insulating layer than the one or more metal layers. In general, such an adaptation may include exposing the semiconductor topography to an etch chemistry comprising hydrogen bromide. In some cases, the etch chemistry may further include a fluorinated hydrocarbon. In yet other embodiments, the method may further or alternatively include using a reactive ion etch process, etching at a relatively low temperature, using a resist mask, and/or using an etch chemistry substantially absent of an oxygen plasma. In this manner, the method may, in some embodiments, include patterning the one or more metal layers using a reactive ion etch process substantially absent of an oxygen plasma.

Abstract: A semiconductor topography is provided which includes a magnetic field shield layer formed upon a semiconductor device. In particular, the semiconductor topography may include a ferromagnetic layer adapted to shield underlying layers from external magnetic fields. Such a ferromagnetic layer may include either ferrite and/or non-ferrite materials. In some embodiments, the semiconductor topography may include a magnetic field shield layer with a different pattern configuration than an adjacent passivation layer. Consequently, a method for processing a semiconductor topography which includes patterning a magnetic field shield layer to form openings other than bond pad openings within the semiconductor topography is provided.

Abstract: A method for oxidizing a semiconductor topography is provided, which includes generating a plasma from a first gas comprising oxygen and a second gas adapted to enhance the generation of oxygen radicals from the first gas. In addition, the method includes extracting the oxygen radicals from the plasma and diffusing the oxygen radicals into one or more layers of the topography. In general, the second gas may include any gas having a component adapted to enhance the generation of oxygen radicals from the first gas. For example, in some embodiments, the second gas may include a gas including nitrogen. In such an embodiment, the ratio of the first gas to the second gas may be adapted to prevent the introduction of nitrogen within the oxidized topography. In addition or alternatively, such a method may include oxidizing a portion of a layer which has a thickness greater than approximately 6 angstroms.

Abstract: A magnetic random access memory (MRAM) device is provided which includes a conductive line configured to induce a magnetic field with a higher magnitude along at least a portion of a magnetic cell junction than along a spacing arranged adjacent to the magnetic cell junction. In some embodiments, the conductive line may include first portions aligned with a plurality of magnetic cell junctions and second portions aligned with spacings arranged between the plurality of magnetic cell junctions. In such an embodiment, the first portions preferably include different peripheral profiles than the second portions. A method for fabricating such an MRAM device is also provided herein. The method may include aligning magnetic cell junctions and first portions of a field-inducing line with each other such that at least part of the first portions of the field-inducing line are configured to conduct a higher density of current than second portions of the field-inducing line.

Abstract: A memory array including a conductive line adapted to simultaneously conduct current in at least two distinct directions relative and adjacent to a magnetic junction is provided. In some embodiments, one of the distinct directions may be substantially aligned with an elongated dimension of the magnetic junction, while another of the distinct directions may be substantially aligned with a shortened dimension of the magnetic junction. In yet other embodiments, at least one of the distinct directions may be aligned at an angle between approximately 0 degrees and approximately 90 degrees relative to an elongated dimension of the magnetic junction. In either case, a memory array is provided which includes a contiguous conductive line having a first portion arranged above a magnetic junction of the memory array and a second portion arranged below the magnetic junction. In addition, a method for operating such a magnetic memory array is provided.

Abstract: A method for reducing the surface roughness of a metal layer is provided. In some embodiments, the method may include depositing a fill layer upon a metal layer and subsequently polishing the fill layer. In some cases, the method may form a surface in which an upper surface of the fill layer is substantially level with at least one of the peaks associated with the surface roughness of the metal layer. In some cases, the surface may include portions of the metal layer and portions of the fill layer residing above the metal layer. In other cases, the method may include forming a surface in which the fill layer is arranged above the metal layer-fill layer interface. In either case, a semiconductor topography having a metal layer with a mean surface roughness less than the mean surface roughness obtained during the deposition of the metal layer may be obtained.

Abstract: A magnetic random access memory (MRAM) device is provided which includes a field-inducing line with a first layer having a plurality of dielectrically spaced conductive segments and a second layer having a conductive portion in contact with at least two of the dielectrically spaced conductive segments. A method for fabricating such a field-inducing layer may include patterning a conductive layer to form the first layer and depositing another conductive layer above at least a portion of the first layer to form the second layer. In some cases, a surface of a first lateral portion of the field-inducing line substantially aligned with a magnetic junction of the device may include a cladding layer, while a surface of a second portion of the field-inducing line substantially aligned with a spacing arranged adjacent to the magnetic junction may be substantially absent of a cladding layer.

Abstract: A method is provided which includes creating a plasma from a gas mixture including diatomic nitrogen gas and a gas comprising silicon. In addition, the method includes exposing a microelectronic topography to the plasma to form a silicon nitride layer thereon. In some cases, the method may include forming the silicon nitride layer at a temperature less than approximately 300° C. Furthermore, the method may include subsequently processing the microelectronic topography at a temperature greater than or equal to approximately 250° C. such that a stress change of less than approximately 1.0×1010 dynes/cm2 occurs within the silicon nitride layer. In addition, a microelectronic topography is provided which has a silicon nitride layer with a concentration of diatomic hydrogen that is at least one order of magnitude lower than a concentration of diatomic hydrogen within a silicon nitride layer formed from a plasma generated from ammonia.

Abstract: A magnetic memory cell and method for improving the write selectivity of memory cells in an MRAM array is provided herein. In particular, the magnetic memory cell may have a magnetic layer with a shape that is substantially asymmetrical about at least one axis of the magnetic layer. Such asymmetry may advantageously reduce and/or eliminate the effects of variations in the fabrication process. In addition, an asymmetrical memory shape may induce a relatively consistent equilibrium vector state, allowing a single switching mechanism to set the magnetic direction of the cell. Furthermore, a method is provided for programming a memory cell, in which the amount of current needed during a writing procedure is advantageously reduced relative to the amount of current needed in conventional writing procedures. In this manner, the asymmetrical memory cell and method produces a storage medium having overall power requirements less than those associated with symmetrical memory cells.

Abstract: A memory circuit which is adapted to identify memory cells within a first time interval for a write operation of the circuit and identify the memory cells within a second time interval for a read operation of the circuit is provided. In some cases, the memory circuit may include an address path which includes a different circuit path for the read operations than for the write operations of the circuit. In addition, the memory circuit may include a means for intentionally delaying the identification of the memory cells for the write operation of the circuit. In some cases, the memory circuit may further include a means for intentionally delaying the identification of memory cells for the read operation of the circuit. Alternatively, the memory circuit may be absent a means for intentionally delaying the identification of memory cells for the read operation of the circuit.

Abstract: A method is provided which includes pulsing power applied to a microelectronic topography between a high level and a low level during a plasma etch process. In particular, the high level may be sufficient to form etch byproducts at a faster rate than a rate of removal of the etch byproducts from the reaction chamber at the high level. In contrast, the low level may be sufficient to form etch byproducts at a rate that is less than a rate of removal of the etch byproducts at the low level. In this manner, an etched topography may be formed without an accumulation of residue upon its periphery. Such a method may be particularly beneficial in an embodiment in which the etch byproducts include a plurality of nonvolatile compounds, such as in the fabrication of a magnetic junction of an MRAM device, for example.

Abstract: A method for reducing the surface roughness of a metal layer is provided. In some embodiments, the method may include polishing the metal layer to a level substantially above any layers arranged directly beneath the metal layer. In some cases, the semiconductor topography comprising the metal layer may be substantially absent of any material laterally adjacent to the metal layer during polishing. In either case, a semiconductor topography having a metal layer with a mean surface roughness less than the mean surface roughness obtained during the deposition of the metal layer may be obtained. As such, the method may include reducing the mean surface roughness of a metal layer. For example, the method may include reducing the mean surface roughness of a metal layer by at least a factor of ten.

Abstract: A circuit is provided herein, which is adapted to supply different current magnitudes along opposing directions of a conductive line. Such a circuit may be particularly beneficial in compensating for the effects of unintentional magnetic coupling within MRAM devices. In addition, a method is provided herein for configuring a device having a magnetic memory array, which receives a first current magnitude along one direction and a substantially different current magnitude along an opposite direction of the magnetic memory array. Furthermore, a method is provided herein which assigns tunable current magnitudes for write operations along conductive lines of a memory circuit. Such tunable writing currents advantageously increase the write selectivity of the memory circuit. More specifically, the tunable writing currents compensate for ferromagnetic and antiferromagnetic coupling within magnetic memory cells caused by uneven surface topology and non-zero total magnetic moments, respectively.

Abstract: A memory array is provided that includes a conductive line adapted to induce a magnetic field around less than all of the magnetic memory junctions arranged along a row or a column of the array. In some cases, the conductive line may be adapted to induce a magnetic field around more than two magnetic memory cell junctions. Alternatively, the conductive line may be adapted to induce a magnetic field around no more than two magnetic memory cell junctions. In either case, the conductive line may include a first portion vertically aligned with one of a plurality of magnetic memory cell junctions and a second portion vertically aligned with another of the plurality of magnetic memory cell junctions. In some embodiments, the second portion may be positioned such that a direction of current flow through the second portion is different than a direction of current flow through the first portion.