Abstract: The invention provides a method for forming bond pad openings through a three-layer passivation structure, which protects the semiconductor device prior to bonding and packaging. Two passivation layers are formed over a semiconductor device with bond pads formed thereon. Openings are formed through the passivation layers to expose the bond pads. The openings are then filled with a photoresist material before depositing a polyimide layer over the passivation layers. Openings are formed in the polyimide layer so as to expose the filled openings. The photoresist material in the filled openings is subsequently removed to expose the bond pads.

Abstract: The present invention provides a new and improved overlay vernier that can increase the overlay measurement accuracy. The overlay vernier of the present invention comprises an inner square vernier and an outer square vernier. The outer vernier comprises a central square opening and four trapezoid-shaped openings surrounding the central square opening.

Abstract: The method of the present invention comprises the steps of: (a) laying on a prior layer, a first oxide layer doped in one form; (b) laying on said first oxide layer, a second oxide layer doped in a different form; (c) patterning said layers; (d) etching the second layer with an etchant having high selectivity to said second doped oxide layer; and (e) etching the first layer with an etchant having high selectivity to said first doped oxide layer. As the etch rate is higher for the highly doped oxide than that for the lightly doped oxide, high selectivity of etching between such layers can therefore be attained. A lightly doped silicon oxide layer may therefore be used to stop etching at an optimal thickness over the complicated layer of substrate. The lightly doped silicon oxide area may be covered with a layer of highly doped silicon oxide layer which may be etched with a specific etchant.

Abstract: The method of the present invention comprises the steps of: (a) laying on a prior layer, a first oxide layer doped in one form; (b) laying on said first oxide layer, a second oxide layer doped in a different form; (c) patterning said layers; (d) etching the second layer with an etchant having high selectivity to said second doped oxide layer; and (e) etching the first layer with an etchant having high selectivity to said first doped oxide layer. As the etch rate is higher for the highly doped oxide than that for the lightly doped oxide, high selectivity of etching between such layers can therefore be attained. A lightly doped silicon oxide layer may therefore be used to stop etching at an optimal thickness over the complicated layer of substrate. The lightly doped silicon oxide area may be covered with a layer of highly doped silicon oxide layer which may be etched with a specific etchant.

Abstract: In a method for the production of semiconductor devices of the type in which a layer of Ti/TiN overlies a layer of fluoro-silicate glass, a layer of material of low dielectric constant is deposited between the layer of Ti/TiN and the layer of fluoro-silicate glass.