Abstract: The invention relates to an electronic system, comprising components and/or units of various kind, hence the electronic system can be called a heterogeneous system and special interfaces therein between. The invented electronic system can be applied in the electric system digital control domain and in particular it is targeting (but not limited to) control of power train of pure electric or hybrid vehicle electric motors that require hard real time and safe control.

Abstract: The invention relates to an electronic system, comprising components and/or units of various kinds, hence the electronic system can be called a heterogeneous system. The invented electronic system can be applied in the electric system digital control domain and in particular it is targeting (but not limited to) control of power train of pure electric or hybrid vehicle electric motors that require hard real time and safe control.

Abstract: The disclosure relates to the field of electric engine digital control domain such as used in the control of vehicle electric motors, including methods related to code handling in the context of debug and/or test and/or calibration or tuning target hardware systems. A method for automated generating of codes, for execution on a heterogeneous hardware system, including software and hardware programmable units, said codes include executable calibration instructions, comprises: (i) loading of initial code, including one or more code descriptions, (ii) providing user calibration instructions, specifying variables in the code descriptions to be considered as calibration parameters and/or monitored values, on said initial code; (iii) a step of automatically generating of said codes, at least one per available unit, based on said loaded initial code, provided with calibration instructions.

Abstract: The invention relates to an electronic system, comprising components and/or units of various kinds, hence the electronic system can be called a heterogeneous system. The invented electronic system can be applied in the electric system digital control domain and in particular it is targeting (but not limited to) control of power train of pure electric or hybrid vehicle electric motors that require hard real time and safe control.

Abstract: The disclosure relates to the field of electric engine digital control domain such as used in the control of vehicle electric motors, including methods related to code handling in the context of debug and/or test and/or calibration or tuning target hardware systems. A method for automated generating of codes, for execution on a heterogeneous hardware system, including software and hardware programmable units, said codes include executable calibration instructions, comprises: (i) loading of initial code, including one or more code descriptions, (ii) providing user calibration instructions, specifying variables in the code descriptions to be considered as calibration parameters and/or monitored values, on said initial code; (iii) a step of automatically generating of said codes, at least one per available unit, based on said loaded initial code, provided with calibration instructions.

Abstract: The invention relates to an electronic system, comprising components and/or units of various kind, hence the electronic system can be called a heterogeneous system and special interfaces therein between. The invented electronic system can be applied in the electric system digital control domain and in particular it is targeting (but not limited to) control of power train of pure electric or hybrid vehicle electric motors that require hard real time and safe control.

Abstract: An embedded field programmable gate array (EFPGA) includes several abuttable configurable logic blocks (ACLBs). Each ACLB is interconnected with adjacent ACLBs by abutment of an out pin to an adjacent in pin. Each ACLB may be an instance of multiple programmable functional blocks. Each ACLB may be a particular ACLB type that provides a particular instance of the multiple programmable functional blocks. The EFPGA may include several ACLBs of the same type. An ACLB of one type may be adjacent an ACLB of a different type. The ACLBs may form sets that are configured identically. The sets may be interconnected by abutment of an out pin to an adjacent in pin. The EFPGA may be part of a system-on-chip integrated circuit. A method for designing an EFPGA with ACLBs that are interconnected by abutment is disclosed.

Abstract: An embedded field programmable gate array (EFPGA) includes several abuttable configurable logic blocks (ACLBs). Each ACLB is interconnected with adjacent ACLBs by abutment of an out pin to an adjacent in pin. Each ACLB may be an instance of multiple programmable functional blocks. Each ACLB may be a particular ACLB type that provides a particular instance of the multiple programmable functional blocks. The EFPGA may include several ACLBs of the same type. An ACLB of one type may be adjacent an ACLB of a different type. The ACLBs may form sets that are configured identically. The sets may be interconnected by abutment of an out pin to an adjacent in pin. The EFPGA may be part of a system-on-chip integrated circuit. A method for designing an EFPGA with ACLBs that are interconnected by abutment is disclosed.

Abstract: An input/output (IO) pad circuitry for integrated circuits (ICs) that is equipped with safety monitoring and control circuits to ensure that signals provided to/from the IO pad behave correctly. The IO pad circuitry allows monitoring of the IO pad signals, the detection of an undesired behavior, e.g., a wrong signal level or a wrong waveform. Furthermore, depending on a selected safety mode, a correction of the IO pad signals by overriding the monitored signal is further achieved. When in full safe mode, signals are provided as required, while in a partial safe mode only certain signals are provided depending on the status. A grouped safe mode allows providing a safe status to a group of IO pads using a single control. A monitoring circuitry between a plurality of input signals to an IC pad is also provided.

Abstract: Field programmable gate arrays (FPGA) contain, in addition to random logic, also other components, such as processing units, multiply-accumulate (MAC) units, analog circuits, and other elements, configurable with respect of the random logic, to enhance the capabilities of the FPGA. A circuit for a filed configurable MAC unit is provided to allow various configurations of ADD, SUBTRACT, MULTIPLY and SHIFT functions. Optionally, registered input and registered output support a multi-cycle path. A configuration of a constant facilitates the configuration of the circuit to perform infinite impulse response (IIR) and finite impulse response (FIR) functions in hardware.