Patents Assigned to Silicon Motion, Inc. (CN)
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Publication number: 20250252051Abstract: The invention introduces a method for garbage collection (GC) in a flash memory device, performed by a processing unit, includes: finding a source block (SBLK) associated with a hit accumulated valid page count (VPC) that is the first one exceeding a total number of physical pages in one destination block (DBLK); labeling the found SBLK and its subsequent SBLKs as first-type SBLKs; labeling the other SBLKs as second-type SBLKs; obtaining Host-address To Flash-address mapping (H2F) sub-tables corresponding to valid pages stored in the second-type SBLKs; in the scanning for each H2F sub-table, detecting valid pages stored in the first-type and the second-type SBLKs, and appending records into a GC table for the valid pages; and reprogramming user data of a designated physical page in a designated first-type or second-type SBLK into a designated physical page in the DBLK according to each record in the GC table.Type: ApplicationFiled: March 21, 2024Publication date: August 7, 2025Applicant: Silicon Motion, Inc.Inventor: Cheng-Yu TSAI
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Patent number: 12367136Abstract: The invention relates to a method, a non-transitory computer-readable storage medium and an apparatus for executing host write commands. The method performed by a processing unit includes: providing a sequential-write command queue (SCQ), a random-write command queue (RCQ) and a mark queue; receiving a host write command from a host side; and pushing a record into the mark queue and pushing the host write command into the SCQ or the RCQ according to a length of the first logical address range carried in the host write command when detecting that a first logical address range carried in the host write command conflicts with a second logical address range carried in at least one sequential write command and/or a third logical address range carried in at least one random write command, where the record indicates that a conflicting sequential write command and/or a conflicting random write command needs to be processed earlier than the host write command.Type: GrantFiled: October 24, 2023Date of Patent: July 22, 2025Assignee: Silicon Motion, Inc.Inventor: Shen-Ting Chiu
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Publication number: 20250231872Abstract: A method for managing a memory apparatus includes: linking a first host address obtained from a received first access command to a first page of a physical block; linking a second host address obtained from a received second access command to at least a second page of the physical block; storing first data of the received first access command and second data of the received second access command into the physical block; building a valid page position table, and storing the valid page position table in a volatile memory; before the pages of the physical block are fully programmed, storing a temporary local page linking address table in the volatile memory; building a global page address linking table according to the linking relationships between the pages of the physical block and the host addresses; and storing the global page address linking table in the volatile memory.Type: ApplicationFiled: March 31, 2025Publication date: July 17, 2025Applicant: Silicon Motion, Inc.Inventors: Tsai-Cheng Lin, Chun-Kun Lee
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Patent number: 12353327Abstract: A method for performing garbage collection (GC) management of a memory device with aid of block classification and associated apparatus are provided. The method may include: utilizing a memory controller to divide at least one portion of blocks among a plurality of blocks into multiple first blocks belonging to at least one first type in a first area and multiple second blocks belonging to at least one second type in a second area; utilizing the memory controller to receive a first command from a host device through a transmission interface circuit within the memory controller; and during writing data in response to the first command, performing a foreground GC procedure to control the memory device to perform GC before completing at least one writing operation corresponding to the first command, for controlling priority of releasing storage space of the second area to be higher than that of the first area.Type: GrantFiled: May 2, 2024Date of Patent: July 8, 2025Assignee: Silicon Motion, Inc.Inventor: Cheng-Yu Tsai
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Patent number: 12353758Abstract: A method used in a flash memory controller includes: using an error correction code (ECC) circuit to perform an ECC operation upon data of a block of a flash memory chip/die of a flash memory device to generate an ECC result; when the ECC result indicates a failure, storing an access task corresponding to the block into a specific buffer; and, controlling a voltage generator of the flash memory device through a specific communication interface to control at least one address decoder of the flash memory device to access the block of the flash memory chip/die again according to at least one threshold voltage level of the voltage generator after the access task has been temporarily stored in the specific buffer for a specific default time.Type: GrantFiled: April 25, 2024Date of Patent: July 8, 2025Assignee: Silicon Motion, Inc.Inventor: Tzu-Yi Yang
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Publication number: 20250217231Abstract: A decoding method includes: using a syndrome calculation check circuit to calculate a syndrome value of variable node Vi of a parity check matrix based on multiple input bits; rotating the syndrome value of variable node Vi into the direction of variable node Vi+1 to generate an estimated syndrome value of variable node Vi+1; rotating the syndrome value of variable node Vi?1 into the direction of variable node Vi?? to generate a rotated syndrome information; performing a weighted-sum calculation based on multiple rotated syndrome information to generate a flipping function value; and comparing the flipping function value with a flipping threshold to generate a flipping result; the syndrome calculation check circuit determines whether to modify/flip a specific bit according to the flipping result.Type: ApplicationFiled: November 11, 2024Publication date: July 3, 2025Applicant: Silicon Motion, Inc.Inventor: Shiuan-Hao Kuo
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Patent number: 12348630Abstract: The invention introduces an apparatus for detecting errors during data encryption. The apparatus includes an encoding circuitry and an error detection circuitry. The encoding circuitry is arranged operably to realize an encryption algorithm including multiple rounds, in which of each round encodes plaintext or an intermediate encryption result with a round key. The error detection circuitry is arranged operably to: calculate redundant data corresponding to the intermediate encryption result; and output an error signal to a processing unit when finding that the intermediate encryption result does not match the redundant data at a check point during an encryption process.Type: GrantFiled: December 7, 2022Date of Patent: July 1, 2025Assignee: Silicon Motion, Inc.Inventors: Wun-Jhe Wu, Po-Hung Chen, Chiao-Wen Cheng, Jiun-Hung Yu, Chih-Wei Liu
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Publication number: 20250211251Abstract: A flash memory storage management method includes: providing a flash memory module including single-level-cell (SLC) blocks and at least one multiple-level-cell block such as MLC block, TLC block, or QLC block; classifying data to be programmed into groups of data; respectively executing SLC programing and RAID-like error code encoding to generate corresponding parity check codes, to program the groups of data and corresponding parity check codes to the SLC blocks; when completing program of the SLC blocks, performing an internal copy to program the at least one multiple-level-cell block by sequentially reading and writing the groups of data and corresponding parity check codes from the SLC blocks to the multiple-level-cell block according to a storage order of the SLC blocks.Type: ApplicationFiled: March 17, 2025Publication date: June 26, 2025Applicant: Silicon Motion, Inc.Inventors: Tsung-Chieh Yang, Hong-Jung Hsu
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Publication number: 20250210106Abstract: A method for performing memory access of a Flash cell of a Flash memory includes: performing an initial sensing operation according to an initial sensing voltage; performing at least a subsequent sensing operation according to a sensing voltage having a value which is higher or lower than the initial sensing voltage according to whether a result of the initial sensing operation is that current flows through the Flash cell; generating a digital value according to the subsequent sensing operation; determining a threshold voltage of the Flash cell according to the generated digital value; and performing soft decoding of the Flash cell according to the determined threshold voltage.Type: ApplicationFiled: March 13, 2025Publication date: June 26, 2025Applicant: Silicon Motion, Inc.Inventors: Tsung-Chieh Yang, Hsiao-Te Chang, Wen-Long Wang
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Publication number: 20250200202Abstract: The invention introduces a method for programming and recovering protected data. Protected data instructed by a data write command is received from a host side in multiple batches. After an encoding algorithm is used to generate an intermediate calculation result according to a first portion of the protected data, and an authentication key, multiple authentication calculation operations for remaining portions of the protected data, and multiple data programming operations for all portions of the protected data are arranged to enable the authentication calculation operations to be performed in parallel to the data programming operations. Each data programming operation is performed to program a corresponding portion of the protected data and a metadata associated with the corresponding portion of the protected data into a current block of a flash module. The metadata comprises information about whether the protected data has passed an authentication.Type: ApplicationFiled: January 19, 2024Publication date: June 19, 2025Applicant: Silicon Motion, Inc.Inventors: Ching-Hung CHEN, Chiu-Han CHANG
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Patent number: 12334168Abstract: A method for performing a test upon a flash memory module includes: performing data writing upon a plurality of first blocks of a first group in the flash memory module; reading the plurality of first blocks of the first group to determine whether there is any abnormal block in the plurality of first blocks and generating a first test result; after the plurality of first blocks are read, performing data writing upon a plurality of second blocks of a second group in the flash memory module; and reading the plurality of second blocks of the second group to determine whether there is any abnormal block in the plurality of second blocks and generating a second test result.Type: GrantFiled: August 22, 2023Date of Patent: June 17, 2025Assignee: Silicon Motion, Inc.Inventors: Chiu-Han Chang, Yu-Ting Chen
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Patent number: 12333155Abstract: A flash memory controller and a data reading method are provided. The flash memory controller includes a control logic circuit and a processor. The control logic circuit is coupled to a first chip-enable-signal controlled area of a flash memory through a channel to transmit data and commands. The processor controls the control logic circuit to transmit a first command and a second command to the first chip-enable-signal controlled area through the channel. The first command is configured to instruct the first chip-enable-signal controlled area to read stored data and read operating temperature information. In response to the transmission of the second command, the processor controls the control logic circuit to receive at least one of the stored data and the operating temperature information from the first chip-enable-signal controlled area.Type: GrantFiled: February 5, 2024Date of Patent: June 17, 2025Assignee: Silicon Motion Inc.Inventors: Hsiao-chang Yen, Tsu-han Lu
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Patent number: 12326808Abstract: The present invention provides a control method of a flash memory controller, which includes the steps of: setting a waiting time in an interrupt coalescing mechanism, and setting a timer, wherein a timeout value of the timer is equal to the waiting time; receiving multiple commands from a submission queue in a host device, generating multiple command responses after processing the multiple commands, and writing the multiple command responses to a completion queue in the host device; receiving a submission queue tail and a completion queue head from the host device; and when the timer reaches the timeout value, subtracting the completion queue head from the submission queue tail to obtain a queue depth of a command queue of the host device.Type: GrantFiled: April 1, 2024Date of Patent: June 10, 2025Assignee: Silicon Motion, Inc.Inventors: Kuo-Han Yuan, Cheng-Yu Tsai
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Patent number: 12327043Abstract: A data storage device includes a memory device and a memory controller. When a sub-region of the memory device is selected based on a predetermined rule to perform a data rearrangement procedure, the memory controller determines whether the selected sub-region is a system data sub-region. When determining that the selected sub-region is not a system data sub-region, the memory controller performs the data rearrangement procedure on the selected sub-region to move data corresponding to logical addresses belonging to the selected sub-region to a memory space of the memory device having continuous physical addresses, and when determining that the selected sub-region is a system data sub-region, the memory controller does not perform the data rearrangement procedure on the selected sub-region.Type: GrantFiled: May 2, 2023Date of Patent: June 10, 2025Assignee: Silicon Motion, Inc.Inventor: Yu-Ta Chen
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Patent number: 12327051Abstract: The present invention provides a flash memory controller configured to access a flash memory module. The flash memory controller includes a transmission interface circuit, a buffer memory and a microprocessor. The transmission interface circuit is coupled to a host device, and the transmission interface circuit includes a time queue, at least one virtual queue and a command processing circuit, wherein the command processing circuit is configured to receive a plurality commands from a host device, write information of the plurality of commands into the time queue in sequence, and write the information of at least part of the plurality of commands into the at least one virtual queue. The buffer memory is configured to store the plurality of commands. The microprocessor is configured to selectively read the time queue or the at least one virtual queue to read the information of the plurality of commands.Type: GrantFiled: April 1, 2024Date of Patent: June 10, 2025Assignee: Silicon Motion, Inc.Inventors: Ming-Yu Tsai, Hong-Ren Fang, Hsin-Ying Teng, Shih-Min Yen
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Patent number: 12321297Abstract: A bridge device for bridging a host device and a data storage device includes a first controller and a second controller. The first controller includes a first transmission interface. The second controller is coupled to the first controller and includes a second transmission interface. The second transmission interface is coupled to the first transmission interface through a bus. The first transmission interface operates in a slave mode and the second transmission interface operates in a master mode. The first transmission interface and the second transmission interface generate multiple transfer data chunks in compliance with a common bridge transfer format to perform transfer operations in dual directions for respectively transferring a command and data between a host device and a data storage device.Type: GrantFiled: July 26, 2023Date of Patent: June 3, 2025Assignee: Silicon Motion, Inc.Inventors: Chen-Hao Chen, Shih-Hsiang Shen, Hui-Lin Liu
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Publication number: 20250156093Abstract: A flash memory controller for controlling a flash memory module includes a communication interface for receiving a first data and a second data; and a processing circuit for dynamically controlling a data writing mode of the flash memory module according to an amount of stored data in the flash memory module. If the amount of stored data in the flash memory module is less than a first threshold when the communication interface receives the first data, the processing circuit controls the flash memory module so that the first data is written into the first data block under an one-bit-per-cell mode. If the amount of stored data in the flash memory module is greater than the first threshold when the communication interface receives the second data, the processing circuit controls the flash memory module so that the second data is written into the second data block under a two-bit-per-cell mode.Type: ApplicationFiled: January 16, 2025Publication date: May 15, 2025Applicant: Silicon Motion, Inc.Inventors: Tsung-Chieh Yang, Chun-Chieh Kuo, Ching-Hui Lin, Yang-Chih Shen
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Patent number: 12292826Abstract: A method for managing a memory apparatus including a non-volatile (NV) memory element having a plurality of physical blocks includes: obtaining a first host address and first data from a first access command; obtaining a second host address and second data from a second access command; linking the first host address to a first page of the physical block and the second host address to a second page of the physical block; storing the first data and second data into the physical block; building a valid page position table and storing the valid page position table in the volatile memory; and building a global page address linking table and storing the global page address linking table in the volatile memory. The valid page position table and the global page address linking table are loaded from the volatile memory and stored to the NV memory element at predetermined time periods.Type: GrantFiled: May 14, 2024Date of Patent: May 6, 2025Assignee: Silicon Motion, Inc.Inventors: Tsai-Cheng Lin, Chun-Kun Lee
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Patent number: 12287973Abstract: An interface circuit includes multiple signal processing devices and a monitor and calibration module. A process monitor monitors a current or a voltage of a test element to generate a process detection result. A temperature monitor monitors an environment temperature to generate a temperature monitored result. A calibration circuit performs calibration operation on a signal processing device according to a preferred reference value subset to adjust a characteristic value of the signal processing device. A compensation control mechanism operation logic selects the preferred reference value subset from multiple reference value subsets according to the process detection result and the temperature monitored result and generates a calibration control signal to control the calibration operation of the calibration circuit.Type: GrantFiled: July 24, 2023Date of Patent: April 29, 2025Assignee: Silicon Motion, Inc.Inventor: Fu-Jen Shih
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Patent number: 12287988Abstract: A technique for accurate communication between a non-volatile memory and its controller. The controller accesses a storage area of the non-volatile memory through data lines, wherein the controller transmits a command through the data lines to access the storage area of the non-volatile memory. The command is further returned from the non-volatile memory to the controller through the data lines for comparison, to determine whether the command is correctly received by the non-volatile memory.Type: GrantFiled: August 3, 2023Date of Patent: April 29, 2025Assignee: SILICON MOTION, INC.Inventors: Hsu-Ping Ou, Chien-Hung Lee