Abstract: The invention introduces an apparatus for segmenting a data stream, installed in a physical layer, to include a host interface, a data register and a boundary detector. The data register is arranged to operably store data received from the host side through the host interface. The boundary detector is arranged to operably detect the content of a data register. When the data register includes a special symbol, the boundary detector outputs a starting address that the special symbol is stored in the data register to an offset register to update a value stored in the offset register, thereby enabling a stream splitter to divide data bits of the data register according to the updated value of the offset register.
Abstract: The invention relates to a method, a non-transitory computer-readable storage medium, and an apparatus for executing an embedded multi-media card (eMMC) command. The method is performed by a processing unit of a flash controller to include: receiving an eMMC command from a host side; and performing a first function associated with a host performance acceleration (HPA) mode according to content of reserved bits of the eMMC command. The HPA mode allows the host side to allocate space in a system memory as an HPA buffer. The HPA buffer stores logical-block-address to physical-block-address (L2P) mapping entries obtained from the flash controller, and each L2P mapping entry stores information indicating which physical address that user data of a corresponding logical address is physically stored in a flash device, thereby enabling the host side to issue an HPA read command carrying the physical address to the flash controller.
Abstract: The present invention provides a control method of a server, wherein the server includes a write buffer for temporarily storing data from an electronic device, the write buffer has a plurality of sectors, and the write buffer has a write pointer and a flush pointer; and the control method comprises: setting each sector to have one of a plurality of states comprising an empty state, a merging state, a need-flush state and a flushing state; and referring to a state of a specific sector indicted by the write pointer to determine if ignoring the specific sector to directly process a sector after the specific sector.
Abstract: A control method is applied to a flash memory controller, which includes the following steps: creating a write time table, wherein the write time table records block numbers of blocks having data stored therein and corresponding first time and second time; referring to the write time table to determine whether there is at least one first block in the flash memory module whose first time is earlier than a first threshold, and if so, recording the at least one first block into an expired block table; referring to the write time table to determine whether there is at least one second block in the flash memory module whose second time is earlier than a second threshold, and if so, recording the at least one second block into the expired block table; and referring to the expired block table to perform an expired block recycling operation.
Abstract: A memory device includes a non-volatile (NV) memory including a plurality of NV memory elements. A method for performing programming management of the NV memory includes: setting a programming sequence of the NV memory elements; determining a selection interval between each of the NV memory elements according to the programming sequence and a serial number of each of the NV memory elements; for a target NV memory element of the plurality of NV memory elements in the programming sequence, determining a serial number of an immediately previous NV memory element in the programming sequence according to the selection interval and a serial number of the target NV memory element; determining whether the immediately previous NV memory element is in a busy state; and only when the immediately previous NV memory element is not in the busy state, programming the target NV memory element.
Abstract: The present invention provides a flash memory controller, wherein the flash memory controller is arranged to access a flash memory module, and the flash memory controller includes a ROM, a microprocessor and a timer. The ROM stores a program code, the microprocessor is configured to execute the program code to control the access of the flash memory module, and the timer is used to generate time information. In the operations of the flash memory controller, the microprocessor refers to the time information to perform dummy read operations upon at least a portion of the blocks, wherein the dummy read operations are not triggered by read commands from a host device.
Type:
Grant
Filed:
June 23, 2021
Date of Patent:
November 1, 2022
Assignee:
Silicon Motion, Inc.
Inventors:
Jian-Dong Du, Chia-Jung Hsiao, Tsung-Chieh Yang
Abstract: The invention is related to a non-transitory computer program product, a method and an apparatus for controlling access to a flash memory card. The method, performed by a processing unit of a bridge integrate circuit (IC), includes: determining whether a temperature of a motherboard has exceeded a threshold through a temperature sensor IC after receiving a host read or write command from a host side; requesting a flash memory card to enter a sleep state when the temperature of the motherboard has exceeded the threshold; and instructing the flash memory card to perform an operation corresponding to the host read or write command when the temperature of the motherboard hasn't exceeded the threshold. The bridge IC and the temperature sensor IC are disposed on the motherboard, the flash memory card is inserted into a card slot on the motherboard, and the bridge IC is coupled to the temperature sensor IC and the flash memory card through a circuit of the motherboard.
Abstract: A flash memory controller includes a read only memory (ROM) and a microprocessor. The ROM is arranged to store a program code. The microprocessor is arranged to execute the program code to control access of a flash memory module. When executing the program code, the microprocessor is arranged to perform operations of: monitoring data retention state of one or more blocks in the flash memory module by reading a last page of the one or more blocks to obtain time information regarding the one or more blocks, which is generated by the flash memory controller; and arranging a specific block to a garbage collection process if time information obtained from the last page of the specific block exceeds a threshold.
Type:
Application
Filed:
June 29, 2022
Publication date:
October 20, 2022
Applicant:
Silicon Motion, Inc.
Inventors:
Jian-Dong Du, Chia-Jung Hsiao, Pi-Ju Tsai
Abstract: The present invention provides a control method of the flash memory controller. In the control method, by establishing a valid page count table, a detailed valid page count table and/or a zone valid page count table according to deallocate command from the host device, the flash memory controller can efficiently and quickly determine if any one of the zones does not have any valid data, so that the flash memory controller can recommend the host device to send a reset command to reset the zone. In addition, after receiving the reset command from the host device, the flash memory controller can use a garbage collection operation or directly put the blocks corresponding to the erased zone into a spare block pool, for the further use.
Abstract: The present invention provides a control method of the flash memory controller. In the control method, after receiving a deallocate command from a host device, the flash memory controller will update a valid page count table, a detailed valid page count table and/or a zone valid page count table according to deallocate command, for the flash memory controller to efficiently and quickly determine if any one of the zones does not have any valid data, so that the flash memory controller can recommend the host device to send a reset command to reset the zone.
Abstract: The present invention provides a control method of the flash memory controller. In the control method, after receiving a deallocate command from a host device, the flash memory controller will update a valid page count table, a detailed valid page count table and/or a zone valid page count table according to deallocate command, for the flash memory controller to efficiently and quickly determine if any one of the zones does not have any valid data, so that the flash memory controller can recommend the host device to send a reset command to reset the zone.
Abstract: The present invention provides a control method of the flash memory controller. In the control method, by establishing a valid page count table, a detailed valid page count table and/or a zone valid page count table according to deallocate command from the host device, the flash memory controller can efficiently and quickly determine if any one of the zones does not have any valid data, so that the flash memory controller can recommend the host device to send a reset command to reset the zone. In addition, after receiving the reset command from the host device, the flash memory controller can use a garbage collection operation or directly put the blocks corresponding to the erased zone into a spare block pool, for the further use.
Abstract: A design technology for backup power of data storage device is disclosed. A development system for a data storage device includes a power supply fixture and a host. The host operates the power supply fixture and a data storage device. The data storage device has a non-volatile memory, a controller and a cache memory. The host operates the power supply fixture to power the data storage device, and operates the power supply fixture to trigger the controller to start a power-loss protection procedure at a first time point. According to the time taken by the power-loss procedure, the host optimizes the capacitance of a capacitor for implementation of a backup power supply to be equipped to the data storage device for production.
Abstract: A low-cost, high-performance data center is shown, which is in a hierarchical and heterogeneous architecture. The data center includes at least three groups of servers, providing three kinds of storage media to store three types of data. The three groups of servers are connected to each other via a computer network. For data with medium access frequency, the corresponding group of servers use multi-level cell solid-state drives as the storage media, and these particular multi-level cell solid-state drives operate in a full-disk pseudo-single-level-cell mode.
Abstract: A memory management method applicable to a data storage device is provided. The memory management method includes steps of: requesting a private memory space from a host; recording a reserved memory space given by the host; dividing a mapping table into a plurality of sub-mapping tables; determining whether a capacity of the reserved memory space is sufficient to store the sub-mapping tables; and if yes, uploading the sub-mapping tables to the reserved memory space via an interface logic.
Abstract: A garbage collection method is provided and applied to a data storage device. The garbage collection method includes the following steps: selecting source blocks from data blocks, wherein a total number of valid data of the source blocks is larger than or equal to a predetermined data number of a block; copying valid data of a part of the source blocks into a destination block, wherein a total number of the valid data of the part of the source blocks is smaller than the predetermined data number; copying all or a part of valid data of remaining source blocks into the destination block; updating a logical to physical addresses mapping table based on a mapping information of the destination block; and recovering all or a part of the source blocks as spare blocks.
Abstract: A method for performing memory access of a Flash cell of a Flash memory includes: performing a plurality of sensing operations respectively corresponding to a plurality of sensing voltages to generate a first digital value and a second digital value of the Flash cell, the second digital value representing at least one candidate threshold voltage of the Flash cell; determining a threshold voltage of the Flash cell according to whether the at least one candidate threshold voltage is high or low; determining soft information of a bit stored in the Flash cell according to the threshold voltage of the Flash cell; and using the soft information to perform soft decoding.
Type:
Application
Filed:
June 5, 2022
Publication date:
September 22, 2022
Applicant:
Silicon Motion, Inc.
Inventors:
Tsung-Chieh Yang, Hsiao-Te Chang, Wen-Long Wang
Abstract: The invention relates to a method for executing host commands, which is performed by a host interface in a flash controller, to include: determining whether a preset number of successive unaligned host long-write commands have been detected, where a first starting logical block address (LBA) number of data to be written, which is requested by each unaligned host long-write command, does not align with a first physical page of one super page; if so, calculating an offset, so that a second starting LBA number of data to be written, which is requested by a host write command, plus the offset aligns with a first physical page of one super page; generating a third starting LBA number by adding the offset to the second starting LBA number; and storing an entry in an LBA shifting table, which includes information about the second starting LBA number and the offset.
Abstract: The invention introduces an apparatus for handling flash physical-resource sets, at least including a random access memory (RAM), a processing unit and an address conversion circuit. The RAM includes multiple segments of temporary space and each segment thereof stores variables associated with a specific flash physical-resource set. The processing unit accesses user data of a flash physical-resource set when executing program code of a Flash Translation Layer (FTL). The address conversion circuit receives a memory address issued from the FTL, converts the memory address into a relative address of one segment of temporary space associated with the flash physical-resource set and outputs the relative address to the RAM for accessing a variable of the associated segment of temporary space.
Abstract: A method for performing memory access management with aid of machine learning in a memory device, the associated memory device and the controller thereof, and the associated electronic device are provided. The method may include: in the memory device, during a training phase, performing machine learning according to a predetermined database regarding threshold voltage distribution, to generate at least one threshold voltage identification model, wherein the at least one threshold voltage identification model is utilized for determining bit information read from a memory cell of the NV memory; and in the memory device, during an identification phase, obtaining representative information of one or more reference voltages when reading the NV memory, for performing machine identification according to the at least one threshold voltage identification model to generate read data, wherein the read data includes the bit information.