Abstract: The invention introduces a method for multi-namespace data access, performed by a controller, at least including: obtaining a host write command from a host, which includes user data and metadata associated with one Logical Block Address (LBA) or more; and programming the user data and the metadata into a user-data part and a metadata part of a segment of a Logical Unit Number (LUN), respectively, wherein a length of the metadata part is the maximum metadata length of a plurality of LBA formats that the controller supports.
Abstract: The invention introduces an apparatus for handling flash physical-resource sets, at least including a random access memory (RAM), a processing unit and an address conversion circuit. The RAM includes multiple segments of temporary space and each segment thereof stores variables associated with a specific flash physical-resource set. The processing unit accesses user data of a flash physical-resource set when executing program code of a Flash Translation Layer (FTL). The address conversion circuit receives a memory address issued from the FTL, converts the memory address into a relative address of one segment of temporary space associated with the flash physical-resource set and outputs the relative address to the RAM for accessing a variable of the associated segment of temporary space.
Abstract: The invention introduces a non-transitory computer program product for handling a sudden power off recovery (SPOR) to include program code to: drive a flash access interface to read pages of a current block in sequence after a power restart subsequent to a sudden power off (SPO); mark the last correct page of the current block according to page read statuses for the current block; drive the flash access interface to read protection information of pages of a temporary block in sequence, so as to mark the first incorrect page of the temporary block; and drop data of the first incorrect page and pages thereafter of the temporary block.
Abstract: The present invention provides a chip comprising a circuit module, a power switch and a detection and control circuit. The power switch is coupled between a supply voltage and the circuit module, and is used to selectively connect the supply voltage to the circuit module, and control a current amount flowing into the circuit module according to at least a control signal. The detection and control circuit is coupled to the power switch, and is used to detect a first signal generated by a first circuit positioned surrounding the circuit module, and compare the first signal with a second signal in a real-time manner to generate the control signal to adjust the current amount flowing into the circuit module.
Abstract: A non-volatile (NV) memory accessing method using data protection with aid of look-ahead processing, and associated apparatus such as memory device, controller and encoding circuit thereof are provided. The NV memory accessing method may include: receiving a write command and data from a host device; obtaining at least one portion of data to be a plurality of messages, to generate a plurality of parity codes through look-ahead type encoding, wherein regarding a message: starting encoding a first partial message to generate a first encoded result; applying predetermined input response information to a second partial message to generate a second encoded result, and combining the first and the second encoded results to generate a first partial parity code; and starting encoding the message to generate a second partial parity code, and outputting the first and the second partial parity codes to generate a parity code; and writing into the NV memory.
Abstract: The present invention provides a method for accessing a secure digital (SD) card, which includes a voltage supply pin for receiving voltage supply from a host, at least one ground pin, a clock pin for receiving a clock signal from a host, a command pin for receiving a command from a host, and four data pins for writing data into the SD card or reading data from the SD card. The method includes receiving, via the command pin, an address extension command including a first address from a host, receiving, via the command pin, an access command including a second address from a host, and accessing, via the data pins, at least a memory location of the SD card indicated by a third address, which is a combination of the first address and the second address. The access command indicates an access operation to be performed on the SD card selected from: a single read operation, a single write operation, a multiple read operation, a multiple write operation and an erase operation.
Abstract: A memory controller and data storage device include a central processing unit, an interface logic circuit and an arbiter circuit. The central processing unit includes an internal memory device. The interface logic circuit is coupled to an external memory device and a standard bus. The arbiter circuit is directly coupled to the central processing unit via an SRAM bus. When the central processing unit has to read predetermined data stored in the external memory device, the central processing unit issues a first request to the interface logic circuit. In response to the first request, the interface logic circuit reads the predetermined data from the external memory device and transmits the predetermined data to the arbiter circuit via the standard bus. The arbiter circuit transfers the predetermined data directly to the central processing unit via the SRAM bus to write the predetermined data in the internal memory device.
Abstract: The present invention provides a method for managing a flash memory module, wherein the flash memory module includes a plurality of flash memory chips, each flash memory chip includes a plurality of first temporary blocks and a plurality of second temporary blocks, each of the first and second temporary blocks and the data blocks includes a plurality of pages, and the method includes: writing data into one of the second temporary blocks; and when an access of the flash memory module meets a specific condition, moving the data stored in the second temporary block to one of the first temporary blocks, and storing information of a first blank page of the second temporary block to the first temporary block.
Abstract: The invention introduces an apparatus for generating a storage mapping table at least including a direct memory access controller for reading first physical location (PL) information corresponding to a logical location of the storage mapping table; an expanding circuit for obtaining the first PL information and expanding the first PL information into second PL information; and a controller for transmitting the second PL information to a host.
Abstract: A data erasing method of a non-volatile memory and a storage device using the same are provided. The data erasing method of the non-volatile memory includes the following steps. A boost circuit is boosted to output a damage voltage. A switch is turned on to apply the damage voltage to the non-volatile memory. The switch is connected between the boost circuit and the non-volatile memory. The non-volatile memory is destroyed by the damage voltage.
Abstract: A circuit test method for a test device to test a device under test is provided. The circuit test method includes the steps of applying zero volts to a plurality of power pins of the device under test; applying a test voltage to a first signal pin among a plurality of signal pins of the device under test; and measuring a current on a second signal pin among the plurality of signal pins of the device under test and determining whether there is a leakage current in the device under test.
Abstract: A method and apparatus for performing dynamic recovery management regarding a RAID are provided. The method includes: writing a first set of protected data into a first protected access unit of multiple protected access units of the RAID, and recording a first set of management information corresponding to the first set of protected data, for data recovery of the first set of protected data; and when any storage device of multiple storage devices of the RAID malfunctions, writing a second set of protected data into a second protected access unit of the protected access units, and recording a second set of management information corresponding to the second set of protected data, for data recovery of the second set of protected data. Any set of the first set of protected data and the second set of protected data includes data and multiple parity-check codes.
Abstract: A method for performing data management in a memory device includes: receiving a set of data from a host device positioned outside the memory device; encoding the set of data according to a first sub-matrix of a predetermined parity-check matrix to generate a partial parity-check code; performing post-processing upon the partial parity-check code according to a predetermined post-processing matrix to generate a parity-check code of the set of data, where the predetermined post-processing matrix is not equivalent to any inverse matrix of a transpose matrix of a second sub-matrix of the predetermined parity-check matrix; and writing/programming a codeword of the set of data into a non-volatile memory of the memory device to allow the memory device to perform error correction when reading the set of data from the non-volatile memory. An associated memory device and a controller thereof are also provided.
Abstract: A method for performing memory access includes: performing a first sensing operation corresponding to a first sensing voltage and performing at least a second sensing operation corresponding to a second sensing voltage to respectively generate a first digital value of a Flash cell of a Flash memory and a second digital value of the Flash cell of the Flash memory; using the first digital value, the second digital value, and charge distribution statistics information of the Flash memory to obtain soft information of a bit stored in the Flash cell, wherein the soft information corresponds to a threshold voltage of the Flash cell; and using the soft information to perform soft decoding.
Type:
Grant
Filed:
October 17, 2019
Date of Patent:
December 1, 2020
Assignee:
Silicon Motion, Inc.
Inventors:
Tsung-Chieh Yang, Hsiao-Te Chang, Wen-Long Wang
Abstract: A memory card controller coupled to a host device includes a processing circuit which is used for reading card specific data from a flash memory of a memory card to store the card specific data in a register wherein a multiply parameter and a basic capacity are marked in the card specific data and used for sending the card specific data to the host device to make the host device calculate a maximum capacity of the memory card according to the multiply parameter and the basic capacity marked in the card specific data.
Abstract: The invention introduces a method for handling sudden power off recovery, performed by a processing unit of an electronic apparatus, to include: driving a flash interface to program data sent by a host into pseudo single-level cell (pSLC) blocks of multiple logical unit numbers (LUNs) in a single-level cell (SLC) mode with multiple channels after detecting that the electronic apparatus has suffered a sudden power off (SPO). The pSLC blocks are reserved from being written any data in regular operations until the SPO is detected.
Abstract: A method for accessing a flash memory module is provided. The flash memory module is a 3D flash memory module including a plurality of flash memory chips, each flash memory chip includes a plurality of blocks, each block includes a plurality of pages, and the method includes: configuring the flash memory chips to set at least a first super block and at least a second super block of the flash memory chips; and allocating the second super block to store a plurality of temporary parities generated when data is written into the first super block.
Abstract: A method for decoding an error correction code and an associated decoding circuit are provided, where the method includes the steps of: calculating a set of error syndromes of the error correction code, where the error correction code is a t-error correcting code and has capability of correcting t errors, and a number s of the set of error syndromes is smaller than t; sequentially determining a set of coefficients within a plurality of coefficients of an error locator polynomial of the error correction code according to at least one portion of error syndromes within the set of error syndromes for building a roughly-estimated error locator polynomial; performing a Chien search to determine a plurality of roots of the roughly-estimated error locator polynomial; and performing at least one check operation to selectively utilize a correction result of the error correction code as a decoding result of the error correction code.
Abstract: The invention introduces a method for reducing data errors in transceiving of a flash storage interface, performed by a processing unit of a first side, comprising: continuously monitoring data frames and/or control frames from a second side; and triggering a TX (transmission) data rate adjustment when information of the data frame and/or the control frame indicates that the lowest layer of the second side detects errors from received data.
Abstract: A non-volatile (NV) memory write method using data protection with aid of pre-calculation information rotation, and associated apparatus such as memory device, controller and encoding circuit thereof are provided. The NV memory write method may include: receiving a write command and data from a host device; obtaining at least one portion of data to be a plurality of messages, to generate a plurality of parity codes through pre-calculation information rotation type encoding, wherein regarding a message: starting encoding a message to calculate a partial parity code according to the message and a transpose matrix of a part-one matrix within a parity check matrix; loading a partial matrix of an inverse matrix of a part-two matrix within the parity check matrix from a storage circuit; applying the partial matrix and its rotated version(s) generated through rotation control to generate and output a corresponding parity code; and writing into the NV memory.