Abstract: When generating a layout for an integrated; circuit (IC) based on a netlist design, a trial layout which need only satisfy the various spatial, power and other constraints, but need not satisfy the layout's timing constraints, is quickly produced. The trial layout acts as a basis for estimating sizes and positions of substrate areas needed to accommodate various modules of the IC and for estimating delays through various signal paths having timing constraints. After producing the trial layout, the IC design is divided into several partitions with modules being grouped into partitions in accordance with their proximity to one another in the trial layout. A floor plan is created which imposes spatial constraints on each partition based on the estimated size and position within the trial layout of the modules forming the partition. A timing budget is also created which allocates portions of each timing constraint to the partitions based on the time delay estimates derived from the trial layout.

Abstract: Disclosed herein is a method for dividing an integrated circuit (IC) design into several circuit partitions, each including one or more circuit modules, and then separately carrying out placement and routing for each circuit partition, with each partition being implemented within a separate area of an IC substrate. The method initially generates a whole-chip trial placement that tends to cluster cells of each circuit module together. An IC substrate floor plan assigning modules to various partitions is prepared, with the size, shape and relative position of each partition being determined by size, shape and relative position of areas of the substrate occupied by those modules in the trial floor plan. A trial routing is also performed with information on which to base a pin assignment plan for each module. A detailed placement and routing process is then independently performed for each partition, with placement and routing of cells within each partition constrained by the floor plan and pin assignment plan.

Abstract: In an integrated circuit (IC) design, a set of K×N clocked IC devices (“syncs”) such as flip-flops and latches are organized into K clusters of N syncs each, with each cluster being clocked by a separate clock tree buffer. An improvement to a conventional “K-center” method for assigning syncs to clusters is disclosed. The improved method, which reduces the separation between syncs within the clusters, initially employs the conventional K-center method to preliminarily assign the K×N syncs to K clusters having N syncs per cluster. The improved method thereafter ascertains boundaries of rectangular areas of the IC occupied by the separate clusters. When areas of any group of M>1 clusters overlap, the K-center meth is repeated to reassign the set of M×N syncs included in e M overlapping clusters to a new set of M clusters. The new set of M clusters are less likely to overlap.

Abstract: CAD software for automated circuit design provides improved display of hierarchical layout. Component placement perimeters are shown with “amoeba” characteristic for improved circuit floor-planning and analysis. Amoeba view of hierarchical design perimeter enables more intuitive observation of circuit floor-plan from actual component placement. Informational brevity conveyed by perimeters of hierarchies in design facilitates simpler interpretation of complex circuit layout, as well as distributed data access to remote sites through email or low-speed network.

Abstract: In computer-aided electronic design automation software, a placement system biases clustering of cells according to their hierarchical design while optimizing placement for controlling die size and total wire length. The placement system also provides for slack distribution, row improvement and randomization during partitioning. Floor plans based on trial placement and placement guiding blocks are also described.