Abstract: Method and apparatus for generating a decode window. A phase locked loop locks a pulse edge of a delayed read data (DRD) signal to an edge of a voltage control oscillator (VCO) clock signal. The edges of the decode window are generated directly from the outer edges of the VCO clock signal. This eliminates errors introduced by quarter cell delay lines, particularly in integrated circuit applications. The transition of the VCO clock signal is used to define a nominal center position coinciding with the mean center position of a data stream. Differential control signals are utilized to shift the VCO transition so that it may be synchronized with the mean bit center position and compensate for non-symmetrical peak jitter. The VCO transition may be shifted without changing the period of the VCO clock signal.