Patents Assigned to Silicon Systems Research Ltd.
  • Sequence error event detection and correction using fixed block digital sum codes
    Patent number: 5938790
    Abstract: A data receiving channel has a signal converter that converts a received signal into a digital signal. The digital signal is then applied to a Viterbi detector that will provide, as an output, a stream of digital signals that have a maximum likelihood of being accurate. Error correction is performed at the bit level through calculation of the error between the received signal and the maximum likelihood estimate signal produced by the Viterbi detector.
    Type: Grant
    Filed: March 4, 1997
    Date of Patent: August 17, 1999
    Assignee: Silicon Systems Research Ltd.
    Inventor: Marcus Marrow