Abstract: A solid state imager includes an arrangement for converting analog pixel values to digital form on an arrayed per-column basis. An N-bit counter supplies an N-bit DAC to produce an analog ramp output providing a ramp signal with a level that varies corresponding to the contents of the counter. Latches or equivalent digital storage elements are each associated with a respective column. A counter bus connects the counter to latch inputs of said latches, and comparators associated the columns gate the latches when the analog ramp equals the pixel value for that column. The contents of the latch elements are transferred sequentially to a video output bus to produce the digital video signal. There can be additionally black-level readout latch elements, for storing a digital value that corresponds to the dark or black video level, and a subtraction element subtracts the black level value from the pixel value to reduce fixed pattern noise. An additional array of buffer latches can be employed.

Abstract: A system for capturing an image includes a CMOS imaging system, an image focusing device, and an image control processing system coupled to the CMOS imaging system. The CMOS imaging system has at least one CMOS imager with at least one series of pixels. The image focusing device directs the image on to at least a portion of the at least one series of pixels. The CMOS imager may have two or more series of pixels at least adjacent each other where each of the series of pixels is offset from another one of the series of the pixels by a reciprocal of the total number of series of pixels in the CMOS imager.

Abstract: A video bus for an array of pixel amplifiers is designed for a minimum quiescent current draw. The pixel amplifiers (or column amplifiers) are designed with high impedance pull-ups and low impedance pull-downs to conserve over-all power dissipation. The video bus is provided with a high-impedance P-FET to reset the bus to drain voltage VDD for a very short time between the time one pixel (or column) is selected the time the next is selected, so that the video bus only has to be discharged through the low impedance N-FET. The bus does not have to be current-sourced by the P-FET.

Abstract: A solid state imager with pixels arranged in columns and rows has the pixels are configured into groups of at least a first pixel and a second pixel, each said group sharing a pixel output transistor having a sense electrode and an output electrode and a reset transistor having a gate coupled to receive a reset signal and an output coupled to the sense electrode of the associated shared pixel output transistor. Each of the pixels has a photosensitive element whose output electrode is coupled to the sense electrode of the shared pixel output transistor and a gate electrode coupled to receive respective first and second pixel gating signals. This configuration reduces the number of FETs to two transistors for each pair of pixels, and also can achieve true correlated double sampling correction of FPN.

Abstract: A bus system which includes two or more voltage-to-current transformers, a common bus, a terminal bus coupled to a voltage source, two or more first switches, and a selection circuit. Each of the voltage-to-current transformers converts a voltage signal to a current signal. The common bus carries the current signals from the voltage-to-current transformers to an output bus. Each of the first switches has a first position where an output from one of the voltage-to-current transformers is coupled to the common bus and a second position where the output is coupled to the terminal bus. The selection circuit is coupled to each of the first switches and controls movement of each of the first switches between the first and second positions.

Abstract: A bus system and an imager for transferring signals from a plurality of signal streams to an output includes a plurality of signal buses in parallel and a control system. The control system multiplexes the signals from two or more of the plurality of signal streams onto two or more of the plurality of signal buses and allows the signals to substantially charge each of the two or more of the plurality of signal buses before demultiplexing the signals to the output. A method for transferring signals includes multiplexing signals on to two or more of a plurality of signal buses and allowing the signals to substantially charge each of the two or more of the plurality of signal buses before demultiplexing the signals to an output.

Abstract: An inverter is implemented in cascode having a first and second NFET and a PFET. The first NFET is biased with a voltage that makes a nearly constant and limited drain-source voltage VDS across the second lower NFET providing a current limiting effect. When an inverter input thereof goes low the PFET will pull the output high normally and the lower NFET is turned off normally. When the inverter input goes high with a normally fast edge, the PFET turns off and the lower NFET pulls the output down. Because of the cascode configuration, the inverter of this embodiment will be current limited and source-drain current is controllable by the bias current. Therefore, a slow and controllable falling edge is produced by this simple circuit. That is, changing the bias voltage applied to the bias terminal changes the slope of the trailing or falling edge of the output waveform. A four transistor implementation and a complementary implementation are possible.