Abstract: Disclosed herein is an SRAM-compatible memory for correcting invalid output data using parity and a method of driving the same. In the SRAM-compatible memory, input data and a parity value obtained from the input data are written in data banks and parity bank, respectively. When invalid data is output from a specific memory bank due to the performance of a refresh operation or other factors, the invalid data are corrected by a data corrector using the parity value written in the parity bank, thus generating output data having the same logic value as the input data. The SRAM-compatible memory prevents a reduction in operation speed due to an internal operation, such as a refresh operation.

Abstract: Disclosed herein are an SRAM-compatible memory and method of driving the SRAM-compatible memory. The SRAM-compatible memory has memory banks, a parity generator and a parity bank. The memory banks each store corresponding one of input data in its DRAM cells specified by an input address. The memory banks perform write operations independently such that when a refresh operation or a write operation for a previous frame is being performed with respect to DRAM cells of a certain memory bank, the write operation of the input data is independently performed with respect to the respective memory banks except for the certain memory bank. The parity generator generates a input parity determined based on the input data and a certain preset parity value. The parity bank stores the input parity.

Abstract: An SRAM-compatible memory device performs a refresh operation with separate fetching and rewriting operation periods.The SRAM-conpatible memory device can be activated by a method of driving the SRAM-compatible memory device. During a first refresh period, the SRAM-compatible memory device performs an operation of fetching data from a DRAM cell to be refreshed. During a second refresh period, the SRAM-compatible memory device performs an operation of rewriting the data fetched during the first refresh period in the refreshed DRAM cell. Accordingly, the length of an assigned refresh period is reduced, and the length of an entire external access period is also reduced.

Abstract: The SRAM-compatible memory device includes a first pair of bit lines for transferring data fetched from/written in a DRAM cell in a first memory block, a second pair of bit lines for transferring data fetched from/written in a DRAM cell in a second memory block. Further, the SRAM compatible memory device includes the first sense amplifier for amplifying and latching data in the first pair of bit lines, a second sense amplifier for amplifying and latching data in the second pair of bit lines, a third sense amplifier for amplifying and latching data transferred whereto, a first switching unit for controlling an electrical connection between the first pair of bit lines and the third sense amplifier, and a second switching unit for controlling an electrical connection between the second pair of bit lines and the third sense amplifier.

Abstract: The synchronous SRAM-compatible memory includes a DRAM array, a data input/output unit, an address input unit, a burst address generating unit, a state control unit, a refresh timer, and a refresh control unit. The data input/output unit controls input and output of data. The address input unit inputs a row address and a column address. The burst address generating unit generates a sequentially varying burst address. The state control unit generates a burst enable signal that enables the burst address generating unit, controls the data input/output unit, and generates a wait indication signal while an access operation of a previous frame is performed with respect to the memory array. The refresh timer generates a refresh request signal activated at regular intervals. The refresh control unit controls the refresh operation with respect to the DRAM array in response to the refresh request signal.

Abstract: Disclosed herein is a synchronous SRAM-compatible memory using DRAM cells. In the synchronous SRAM-compatible memory of the present invention, a refresh operation is controlled in response to a refresh clock signal having a period “n” times a period of a reference clock signal. The refresh operation is performed while a chip enable signal/CS is inactivated. A writing/reading access operation is performed in response to a writing/reading command generated while the chip enable signal/CS is activated. Therefore, in the writing/reading access operation of the synchronous SRAM-compatible memory of the present invention, no delay of time occurs that would otherwise occur due to the refresh operation of the DRAM cells.

Abstract: An easily implemented SRAM compatible memory device usable as a low power asynchronous SPRAM and a driving method therefor. The method for driving the SRAM compatible memory device includes the steps of (a) inputting a leading address designating at least one of the plurality of memory cells, (b) generating an address transition detection signal in response to the input leading address, (c) allowing a predetermined DRAM access time to elapse after generation of the address transition detection signal, (d) performing an access operation of the DRAM memory array for the duration of the DRAM access time after step (c), and (e) inputting a lagging address different from the leading address after the lapse of a predetermined SRAM access time from the leading address input time. The SRAM access time is equal to or longer than twice the DRAM access time.